Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

A protective film forming agent that, in dicing of a semiconductor wafer, is used to form a protective film on the surface of the semiconductor wafer, can form a protective film that has excellent laser processability, and has excellent solubility of a light-absorbing agent; and a method for producing a semiconductor chip using the protective film forming agent. The protective film forming agent includes a water-soluble resin, a light-absorbing agent, a basic compound, and a solvent. The basic compound is an alkylamine, an alkanolamine, an imidazole compound, ammonia, or an alkali metal hydroxide. The light-absorbing agent content of the protective film forming agent is 0.1-10 mass % (inclusive).

Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.

An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. The width of the lower conductive section on a first boundary between the lower and upper conductive sections in the first direction is greater than the width of the upper conductive section on the first boundary in the first direction and the width of the second conductive pattern on a second boundary between the contact plug and the second conductive pattern in the first direction.

A device and method of manufacturing a semiconductor device with integrated photonic and electronic components is described. The method may include: providing a silicon-on-insulator (SOI) wafer having a silicon handle wafer, a buried oxide (BOX) layer, and a silicon waveguide layer; forming a photonic integrated circuit (PIC) including one or more of the waveguide or a metal layer; removing the silicon wafer to expose the BOX layer; and extending the BOX layer by one or more of: depositing oxide and planarizing onto the BOX layer to increase BOX layer thickness to an extended BOX layer, or fusion bonding a second wafer with a surface oxide layer. The device may include a photonic integrated circuit (PIC), an additional oxide layer, and an integrated optical component positioned to reflect or reshape optical signals within a waveguide layer vertically.

A semiconductor device includes a chip, an electrode that is formed on the chip, an inorganic insulating layer that covers the electrode and has a first opening exposing the electrode, an organic insulating layer that covers the inorganic insulating layer, has a second opening surrounding the first opening at an interval from the first opening, and exposes an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and an Ni plating layer that covers the electrode inside the first opening and covers the inner peripheral edge of the inorganic insulating layer inside the second opening.

The present application relates to a semiconductor fin structure cut process. The process includes: providing a semiconductor substrate and forming a plurality of fin structures on the semiconductor substrate, a gap being formed between every two adjacent fin structures; depositing a first dielectric layer, the first dielectric layer being filled in the gaps so that all fin structures are connected into a whole to form a semiconductor with fins; forming a plurality of pattern layer strips on the semiconductor with fins, a groove being formed between every two adjacent pattern layer strips, the fin structures closest to each pattern layer strip in the semiconductor with fins being necessary fin structures, attaching mask strips onto side surfaces of each pattern layer strip, the mask strips covering the necessary fin structures; etching the semiconductor with fins so that the unnecessary fin structures not covered by the mask strips are truncated.

Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

An etching method includes: (a) providing a substrate including an etching target film and a mask on the etching target film; (b) after (a), forming a metal-containing deposit on the mask by a first plasma generated from a first processing gas including a metal-containing gas and a hydrogen-containing gas; (c) after (b), deforming or modifying the metal-containing deposit by a second plasma generated from a second processing gas different from the first processing gas; and (d) after (c), etching the etching target film.