A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

The present disclosure discloses a semiconductor device and a fabrication method thereof. In the method, firstly etching a substrate in a first device region to form at least one first trench and then etching the substrate in both first device region and second device region to form at least one first isolation trench at the positions corresponding to the at least one first trench and form at least one second isolation trench in the second device region. Herein a depth of the first isolation trench is larger than that of the second isolation trench.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.

Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a semiconductor substrate. The semiconductor substrate includes a base portion, a semiconductor bar portion on a first active area of the base portion, a set of semiconductor branch portions extending from a sidewall of the semiconductor bar portion to a second active area of the base portion, and first and second isolation structures formed on the second active area of the base portion. The first interface between the first isolation structure and the semiconductor bar portion is flat. The second interface between the second isolation structure and the semiconductor bar portion is flat. The first interface and the second interface are staggered from each other along the extending direction of the semiconductor bar portion.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.

A method of manufacturing a plurality of chips by dividing a workpiece having a substrate harder than a monocrystalline Si substrate includes a cut groove forming step of, while holding the workpiece on a holding table with a surface of the workpiece being exposed, cutting the workpiece along each of projected dicing lines with a first cutting blade as it is vibrating at a frequency in the ultrasonic band, to form a cut groove in the workpiece such that the cut groove extends from the surface of the workpiece and terminates short of another surface of the workpiece, and a dividing step of, while holding the workpiece on the holding table with the other surface of the workpiece being exposed, cutting off an uncut residual portion from the workpiece along each of the lines with a second cutting blade to divide the workpiece into a plurality of chips.