A resist underlayer film forming composition which has high storage stability, has a low film curing start temperature, can cause the generation of a sublimated product in a reduced amount, and enables the formation of a film that is rarely eluted into a photoresist solvent; a method for forming a resist pattern using the resist underlayer film forming composition; and a method for manufacturing a semiconductor device. The resist underlayer film forming composition includes a crosslinkable resin, a crosslinking agent, a crosslinking catalyst represented by formula (I) and a solvent. (A-SO.sub.3).sup.(BH).sup.+[wherein A represents a linear, branched or cyclic saturated or unsaturated aliphatic hydrocarbon group which may be substituted, an aryl group which may be substituted by a group other than a hydroxy group, or a heteroaryl group which may be substituted; and B represents a base having a pKa value of 6.5 to 9.5.]

A method may include providing a semiconductor substrate, comprising a first layer of a first thickness dopant, a first dopant polarity, and a first dopant concentration; and a second layer having a second thickness greater than the first thickness, a second polarity, and second dopant concentration, wherein the second layer defines a second dopant concentration, greater than the first dopant concentration. The method may further include forming a separation diffusion region having a dopant of the second dopant polarity around a periphery of the first layer, where the separation diffusion region extends from a first surface to a separation depth, greater than the first thickness of the first layer. The method may also include performing a thinning of the semiconductor substrate by removing a portion of the second layer from the second surface, wherein after the thinning, the second layer comprises a third thickness, less than the first thickness.

A method of processing a monocrystalline semiconductor work piece includes: applying pulses of laser light to a first main surface of the monocrystalline semiconductor work piece, the pulses of laser light penetrating the first main surface and forming modified regions in a separation zone within the monocrystalline semiconductor work piece, each modified region being delimited by a subcritical crack that surrounds an inner part in which the monocrystallinity of the semiconductor work piece is altered; controlling the pulses of laser light such that the subcritical cracks of adjacent ones of the modified regions are non-overlapping for at least half of the modified regions formed in the monocrystalline semiconductor work piece; and after inducing the subcritical cracks, forming at least one crack that connects the subcritical cracks. Additional work piece splitting techniques and techniques for compensating work piece deformation that occurs during the splitting process are also described.

A technique improves etch selectivity. An etching includes (a) providing, in a chamber, a substrate including an underlying film and a silicon-containing film on the underlying film, (b) etching the silicon-containing film to form a recess with first plasma generated from a first process gas containing a hydrogen fluoride gas until before the underlying film is exposed at the recess or until the underlying film is partly exposed at the recess, and (c) further etching the silicon-containing film at the recess under a condition different from a condition of (b).

The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

A method for manufacturing a semiconductor structure is provided. A first mask layer and a photoresist layer are formed over a substrate, wherein photosensitivities of the photoresist layer and the first mask layer are different. A first and a second opening are formed, wherein the first mask layer overlapped by the second opening is degraded to form a second mask layer. The substrate exposed by the first opening is partially removed to form a first recess of the substrate. The second mask layer is removed to form a third opening through the first mask layer. A first dielectric layer is formed, wherein the first dielectric layer fills the first recess and the third opening and covers the substrate overlapped by the third opening. A patterning operation is performed on the substrate using the first dielectric layer as a mask, and a second recess of the substrate is thereby formed.

The disclosure provides a method of patterning a semiconductor structure. A first composite substrate including first spacers on a first substrate and a second composite substrate including second spacers on a second substrate are received. The second composite substrate is disposed on the first composite substrate, in which at least one of the first spacers is in direct contact with at least one of the second spacers. Spaces between the first spacers and the second spacers are filled with a directed self-assembly material, in which the directed self-assembly material includes first portions between the first spacers and the second substrate, second portions between the second spacers and the first substrate, and third portions being remaining portions. The second composite substrate, the first spacers, and the first portions and the second portions are removed. Oxide layers are filled between the third portions. The third portions are removed.

A FET channel includes a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also includes a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

A manufacturing method of a semiconductor device includes depositing a first bilayer structure over a substrate, in which the first bilayer structure includes a silicon oxide layer and a silicon nitride layer over the silicon nitride layer; forming a first carbonaceous hard mask on the first bilayer structure; forming a second bilayer structure on the first carbonaceous hard mask; forming a mask stack of alternating anti-reflecting coating (ARC) hard masks and second carbonaceous hard masks on the second bilayer structure; and coating a photoresist on the mask stack.