A manufacturing method of a semiconductor device includes depositing a first bilayer structure over a substrate, in which the first bilayer structure includes a silicon oxide layer and a silicon nitride layer over the silicon nitride layer; forming a first carbonaceous hard mask on the first bilayer structure; forming a second bilayer structure on the first carbonaceous hard mask; forming a mask stack of alternating anti-reflecting coating (ARC) hard masks and second carbonaceous hard masks on the second bilayer structure; and coating a photoresist on the mask stack.

An embodiment relates to a method obtaining a silicon carbide wafer comprising a first conductivity type substrate and a first conductivity type drift layer, forming a second conductivity type first well region within the first conductivity type drift layer, forming a first conductivity type source region within the second conductivity type first well region, forming a second conductivity type plug region under the first conductivity type source region, forming a gate oxide layer, forming a patterned gate metal layer, depositing an interlevel dielectric (ILD) layer, forming a first patterned mask layer on top of the ILD layer, and etching the ILD layer and the first conductivity type source region using the first patterned mask layer, and forming a silicide layer, wherein the silicide layer is in contact with a vertical sidewall of the first conductivity type source region and at-least one second conductivity type region.

An embodiment relates to a method obtaining a silicon carbide wafer comprising a first conductivity type substrate and a first conductivity type drift layer, forming a second conductivity type first well region within the first conductivity type drift layer, forming a first conductivity type source region within the second conductivity type first well region, forming a second conductivity type plug region under the first conductivity type source region, forming a gate oxide layer, forming a patterned gate metal layer, depositing an interlevel dielectric (ILD) layer, forming a first patterned mask layer on top of the ILD layer, and etching the ILD layer and the first conductivity type source region using the first patterned mask layer, and forming a silicide layer, wherein the silicide layer is in contact with a vertical sidewall of the first conductivity type source region and at-least one second conductivity type region.

A semiconductor structure includes a substrate, at least one first fin protruded from the substrate, and a 3D capacitor disposed over the substrate. The 3D capacitor includes a doped electrode conformally disposed in the first fin, a metal electrode disposed over the doped electrode, and a dielectric layer disposed between the doped electrode and the metal electrode.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

A multilayer wiring connection structure and a method for manufacturing the same are provided. The multilayer wiring connection structure includes a first insulating film positioned on a substrate, a first wiring positioned within the first insulating film, a second insulating film positioned on the first wiring, and a second wiring positioned within the second insulating film and in contact with the first wiring. The first wiring comprises a trench having at least one anisotropically etched portion and at least one isotropically etched portion under the second wiring, and the second wiring comprises an extension filling the trench.

A substrate processing method is provided and includes forming a laminated structure film over a substrate, the laminated structure film including a metal-containing layer and a halogen-containing layer that are laminated; irradiating the laminated structure film with extreme ultraviolet light in a predetermined pattern to form, in the laminated structure film, an exposed portion irradiated with the extreme ultraviolet light and an unexposed portion not irradiated with the extreme ultraviolet light; and selectively removing the exposed portion of the laminated structure film.

A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about 100 MPa to about 100 MPa.

The present disclosure provides a method for improving residue formation after mandrel removal, including steps of: providing a TEOS layer, forming mandrel structures spaced apart from each other on the TEOS layer, and forming spacers on sidewalls of each of the mandrel structures; forming a first SOC layer to cover the surface of the TEOS layer, the mandrel structures, and the spacers of the mandrel structures, and forming a SOC structure that covers the spacers and exposes the top surfaces of the mandrel structures; removing the mandrel structures by etch along sidewalls of SOC structure, forming a first groove between two of the spacers on the sidewalls of the removed mandrel structures; forming a second SOC layer to cover the SOC structure and fill the first groove; performing top planarization of the second SOC layer until the top surface of the SOC structure is exposed.

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.