H10P74/00

Methods of determining a height, and a height profile, of a wire loop on a wire bonding machine

A method of determining a height value of a wire loop on a wire bonding machine is provided. The method includes the steps of: (a) imaging at least a portion of a wire loop using an imaging system on a wire bonding machine to detect a path of the portion of the wire loop; (b) moving a wire bonding tool towards a first contact portion of the wire loop in the path; (c) detecting when a portion of a conductive wire engaged with the wire bonding tool contacts the first contact portion of the wire loop; and (d) determining a height value of the wire loop at the first contact portion based on a position of the wire bonding tool when the portion of the conductive wire contacts the first contact portion of the wire loop.

PROBE AND ELECTRICAL CONNECTION DEVICE
20260056233 · 2026-02-26 ·

A probe includes: a tip member including a contact portion and a base end portion connected to the contact portion; a main body in which the base end portion is embedded in an end portion; and a first reinforcing member arranged on a side surface of the main body so as to overlap with at least a part of the base end portion. The base end portion is embedded in the end portion of the main body so as to expose the contact portion. The first reinforcing member is continuously arranged on a side surface of the main body from an embedded region in which the base end portion is embedded to a region around the embedded region.

Operating method of electronic device configured to support manufacturing semiconductor device, and operating method of semiconductor manufacturing system including electronic devices configured to support manufacturing semiconductor dies

A method of operating an electronic device that is configured to support manufacturing a semiconductor device includes (i) selecting a height of a stage of the electronic device that is configured to hold the semiconductor device, (ii) generating white light by using a light source of the electronic device, (iii) generating light of a selected wavelength by filtering the white light using a monochromater of the electronic device, (iv) emitting the light of the selected wavelength to the semiconductor device using a beam splitter of the electronic device, and (v) capturing reflection light reflected from the semiconductor device using a camera of the electronic device.

GALLIUM NITRIDE SUBSTRATE

A gallium nitride substrate has a main surface inclined by 0 to 20 from a (0001) plane and having an area of 15 cm.sup.2 or more. The main surface has a dislocation density of 510.sup.6 cm.sup.2 or less, and a number density of local strains in a crossed Nicols image obtained by a sensitive color method for the main surface is 0.5 cm.sup.2 or less.

Wafer positioning method and apparatus

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Semiconductor test key including strip arranged resistor patterns

The invention provides a semiconductor testkey, which includes a testkey on a substrate, the testkey includes a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.

Semiconductor element, semiconductor device including the semiconductor element, and semiconductor element manufacturing method
12557605 · 2026-02-17 · ·

Provided is a semiconductor element including a semiconductor substrate; a semiconductor layer laminated to the semiconductor substrate, and having a circuit formed within the semiconductor layer; a conductive layer disposed on an opposite side of the semiconductor layer from the semiconductor substrate and including a part electrically connected to the circuit; and a conductive portion disposed between the semiconductor layer and the conductive layer, and electrically connected to the conductive layer. The conductive layer includes a check pattern not electrically connected to the circuit, and the conductive portion includes a superimposition portion superimposed on the check pattern as viewed in a thickness direction of the semiconductor substrate.

Degradation circuit

One example discloses a degradation circuit, including: a first structure configured to be coupled to an integrated circuit (IC); a second structure, coupled to the first structure, and configured to be coupled to the IC; wherein together the first and second structures form a degradation detection element; and a controller, coupled to the degradation detection element, and configured to set an operational state of the IC based on the degradation detection element.

Laser repair method and laser repair device
12557603 · 2026-02-17 · ·

A laser repair method includes a repair process of performing repair work by setting a laser radiation range for a defect part in a multi-layer film substrate and irradiating the defect part with a laser beam under set laser working conditions. In the repair process, spectrum data of the defect part is acquired, and the laser working conditions of the laser beam, with which the defect part is to be irradiated, are set using a neural network after learning on the basis of the spectrum data, and the neural network has undergone machine learning using, as learning data, measurement data including multi-layer film structure data, spectrum data of each multi-layer film structure, and laser working experimental data of each multi-layer film structure.

Defect density calculation method, defect-density calculation program, defect-density calculation apparatus, heat treatment control system and machining control system

A defect density calculation method according to one embodiment of the present disclosure is a method of calculating a temporal change of the defect density distribution in a semiconductor layer. The method includes calculating the temporal change of the defect density distribution on the basis of an arithmetic function using at least the activation energy of a detect included in the semiconductor layer, the processing temperature of the semiconductor layer, and the processing time of the semiconductor layer as arguments.