An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.

The invention relates to a method for annealing of at least two wafers bonded via low-temperature direct bonding comprising heating the bonded wafers up to a first annealing temperature in the range of 100 C. to 500 C., preferably 150 C. to 400 C., even more preferred 150 C. to 200 C., holding the first annealing temperature in a range of 1 to 4 hours, preferably 1 to 3 hours, cooling down the bonded wafers to room temperature, re-heating the bonded wafers to a second annealing temperature in the range of 100 C. to 500 C., preferably 150 C. to 400 C., even more preferred 150 C. to 200 C., and cooling down the bonded wafers to room temperature.

A method for hydrophilic direct bonding of a first substrate onto a second substrate is provided, including: providing the first substrate having a first main surface and the second substrate having a second main surface; bringing the first and the second substrates into contact with one another, respectively, via the first and the second main surfaces, to form a bonding interface between two bonding surfaces; applying a heat treatment to close the bonding interface; and prior to the step of bringing the first and the second substrates into contact, forming, on the first main surface and/or on the second main surface, a bonding layer made of an amorphous semiconductor material having doping elements and a thickness of less than or equal to 50 nm, a face of the bonding layer constituting one of the two bonding surfaces, an oxide layer being less than 20 nm from the bonding interface.

A wafer is processed by causing a cutting blade to cut into an outer circumferential surplus region of a first wafer from the front surface side by a predetermined thickness and executing cutting along the outer circumferential edge to form an annular step part in the outer circumferential surplus region, bonding the front surface side of the first wafer and the front surface side of a second wafer to form a bonded wafer, forming an annular modified layer by positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the first wafer to the inside of the first wafer and executing irradiation with the laser beam along the boundary between a device region and the outer circumferential surplus region from the back surface side, and grinding the back surface side of the first wafer to execute thinning to a predetermined finished thickness.

A method for forming a high resistivity handle substrate for a composite substrate comprises: providing a base substrate made of silicon; exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer having a thickness of at least 10 nm on the surface of the base substrate; and then growing a polycrystalline charge trapping layer on the carbon-containing layer.

A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.

A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: regions of direct contact between the working layer and the carrier substrate; and agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.

A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: regions of direct contact between the working layer and the carrier substrate; and agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.

A method for detecting impurities on a surface of a silicon wafer for manufacturing semiconductors, the impurities not being able to be detected by a conventional inspection method, a method for manufacturing the silicon wafer for manufacturing semiconductors having the impurities removed from the surface thereof, and a method for screening wafers for manufacturing semiconductors. This method for detecting impurities on a surface of a wafer for manufacturing semiconductors includes: a step for coating the surface of the wafer with a film-forming composition, and performing baking to form a film; and then a step for detecting impurities by means of a wafer inspection tool.

A method for detecting impurities on a surface of a silicon wafer for manufacturing semiconductors, the impurities not being able to be detected by a conventional inspection method, a method for manufacturing the silicon wafer for manufacturing semiconductors having the impurities removed from the surface thereof, and a method for screening wafers for manufacturing semiconductors. This method for detecting impurities on a surface of a wafer for manufacturing semiconductors includes: a step for coating the surface of the wafer with a film-forming composition, and performing baking to form a film; and then a step for detecting impurities by means of a wafer inspection tool.