A first transfer device and a second transfer device are configured to transfer a first substrate and a second substrate in a normal pressure atmosphere. A third transfer device is configured to transfer the first substrate and the second substrate in a decompressed atmosphere. A load lock chamber has accommodation sections allowed to accommodate therein the first substrate and the second substrate, and is allowed to switch an inside of the accommodation sections between the normal pressure atmosphere and the decompressed atmosphere. Multiple gates are respectively disposed on three different sides of the load lock chamber, and allowed to open or close the load lock chamber. The first transfer device, the second transfer device, and the third transfer device carry the first substrate and the second substrate into/out of the load lock chamber through different gates among the multiple gates.

A composite substrate includes a substrate, a high-resistance layer located on the substrate, the high-resistance layer comprising a first low-temperature aluminum nitride (AlN) layer, a high-temperature AlN layer and a second low-temperature AlN layer which are stacked in sequence, and a growth substrate located on a side, away from the substrate, of the high-resistance layer. Under the action of the first low-temperature AlN layer, a tensile stress on the high-temperature AlN layer may be reduced, to reduce a dislocation, and further improve a crystal quality of the high-temperature AlN layer and ensure resistivity of the high-temperature AlN layer; and an element of Al in the high-temperature AlN layer is prevented from diffusing into the growth substrate, to protect the crystal quality of the high-temperature AlN layer and improve a bonding effect between the high-resistance layer and the growth substrate. Thus, stability and reliability of the composite substrate are greatly improved.

A method for wafer treatment is disclosed. A wafer is provided with a main surface, a surface layer, and a base layer. The surface layer is disposed between the main surface and the base layer, and the surface layer covers the base layer and exposes the main surface. Then, at least one laser process is performed to fully irradiate the main surface and the surface layer with a first laser to generate a plurality of optimized regions in the main surface and the surface layer, so that the optimized regions form at least one stress-relieving array.

A method for wafer treatment is disclosed. A wafer is provided with a main surface, a surface layer, and a base layer. The surface layer is disposed between the main surface and the base layer, and the surface layer covers the base layer and exposes the main surface. Then, at least one laser process is performed to fully irradiate the main surface and the surface layer with a first laser to generate a plurality of optimized regions in the main surface and the surface layer, so that the optimized regions form at least one stress-relieving array.

A method of processing a bonded wafer formed by bonding a first wafer and a second wafer to each other via a bonding layer includes a coordinate generating step of generating coordinates of an undersurface position of the first wafer, the undersurface position being to be irradiated with laser beams, such that an end position of a crack extending from modified layers formed within the first wafer is located at an outer circumference of the bonding layer, and a modified layer forming step of forming a plurality of modified layers in a ring shape by irradiating the coordinates generated in the coordinate generating step with the laser beams of a wavelength transmissible through the first wafer.

A processing method of a bonded wafer includes forming a plurality of modified layers in a form of rings through positioning focal points of laser beams with a wavelength having transmissibility with respect to a first wafer inside the first wafer, from which a chamfered part is to be removed, from a back surface of the first wafer and executing irradiation, holding a second wafer side on a chuck table, and grinding the back surface of the first wafer to thin the first wafer. In the forming the modified layers, the focal points of the laser beams are set in such a manner as to gradually get closer to a joining layer in a direction from an inner side of the first wafer toward an outer side thereof, so that the plurality of ring-shaped modified layers are formed in a form of descending stairs.

A method of making a silicon-on-insulator (SOI) device from a bulk silicon substrate and an SOI device are disclosed. In the method, a stack of a heteroepitaxial layer and a silicon epitaxial layer are formed on a bulk silicon substrate, and a first photolithography process is performed on the stack to form a first trench exposing the bulk silicon substrate. The first trench is filled with a first isolation dielectric, and a second photolithography process is performed on the stack to form a second trench. The first isolation dielectric and the second trench isolate the stack. Subsequently, the heteroepitaxial layer is removed from the stack, forming at least one cavity. Moreover, the at least one cavity is filled with a buried oxide layer. The buried oxide layer and the silicon epitaxial layer overlying the buried oxide layer form SOI substrate structures. SOI devices are formed on the SOI substrate structures.

A method of forming a support substrate having a charge-trapping layer involves introducing a single-crystal silicon base substrate into a deposition chamber and, without removing the base substrate from the chamber and while flushing the chamber with a precursor gas, forming an intrinsic silicon epitaxial layer on the base substrate, then forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period, and then forming a polycrystalline silicon charge-trapping layer on the dielectric layer by introducing a precursor gas into the chamber over a second time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature of between 1010 C. and 1200 C.

Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and/or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1 C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds. The example techniques can direct-bond lithium tantalate LiTaO.sub.3 to various conventional substrates in a process for making various novel optical and acoustic devices.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).