Disclosed are a circuit device and a display device including the same. The circuit device may include a board, an electronic component mounted on the board, an IC chip meeting an upper surface of the electronic component, and a coating layer partially surrounding a side surface of the electronic component and having an upper surface spaced apart from the IC chip.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

The present invention provides an electronic or electrical device or component thereof comprising a cross-linked polymeric coating on a surface of the electronic or electrical device or component thereof; wherein the cross-linked polymeric coating is obtainable by exposing the electronic or electrical device or component thereof to a plasma comprising a monomer compound and a crosslinking reagent for a period of time sufficient to allow formation of the cross-linked polymeric coating on a surface thereof, wherein the monomer compound has the following formula: ##STR00001##
where R.sub.1, R.sub.2 and R.sub.4 are each independently selected from hydrogen, optionally substituted branched or straight chain C.sub.1-C.sub.6 alkyl or halo alkyl or aryl optionally substituted by halo, and R.sub.3 is selected from: ##STR00002##
where each X is independently selected from hydrogen, a halogen, optionally substituted branched or straight chain C.sub.1-C.sub.6 alkyl, halo alkyl or aryl optionally substituted by halo; and n.sub.1 is an integer from 1 to 27; and wherein the crosslinking reagent comprises two or more unsaturated bonds attached by means of one or more linker moieties and has a boiling point at standard pressure of less than 500 C.

A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

A package structure according to the present disclosure includes a bottom substrate, a bottom interconnect structure over the bottom substrate, a top interconnect structure disposed over the bottom interconnect structure and including a metal feature, a top substrate over the top interconnect structure, and a protective film disposed on the top substrate. The protective film includes an interfacial layer on the top substrate, at least one dipole-inducing layer on the interfacial layer, a moisture block layer on the at least one dipole-inducing layer, and a silicon oxide layer over the moisture block layer. The at least one dipole-inducing layer includes aluminum oxide, titanium oxide or zirconium oxide.

A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.

Semiconductor devices including seal rings and method of making the same is provided. A semiconductor device comprises an interconnect layer over a substrate. The interconnect layer comprises a barrier layer over a dielectric layer. A seal ring is in the interconnect layer and the seal ring extends through the interconnect layer to abut the substrate. An insulator layer is around the seal ring and the insulator layer spaces the seal ring from the barrier layer. A protective structure is laterally adjacent to the seal ring and the protective structure extends through the interconnect structure to abut the substrate. The seal ring may be segmented and comprises a first segment in a first trench in an interconnect stack, and a second segment in a second trench in the interconnect stack.

Provided is a semiconductor device including a substrate, a channel layer on the substrate and having a first material, a barrier layer located on the channel layer and including a second material having an energy band gap different from that of the first material, a gate electrode located on the barrier layer and extending in a first direction, a gate semiconductor layer located between the barrier layer and the gate electrode, a source electrode connected to the channel layer and spaced apart from the gate electrode in a second direction perpendicular to the first direction, a drain electrode connected to the channel layer and spaced apart from the gate electrode in the second direction in the second direction, and a crack propagation prevention structure located on a side of the source electrode and connected to the source electrode, and penetrating through the channel layer and the barrier layer into the substrate.

The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region surrounding the circuit region, and a dicing lane surrounding the seal ring region, wherein the dicing lane includes a first dicing region and a second dicing region disposed on both sides of the first dicing region; first active regions formed in the circuit region; first gate stacks formed on the first active region in the circuit region, the first gate stacks including metal electrodes; second active regions formed in the first dicing region; dielectric structures formed on the second active regions in the first dicing region; and second gate stacks formed on an isolation feature in the second dicing region.

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 m; and electrically connecting the first landing pad to one of the two electrodes.