A semiconductor device according to an embodiment includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate includes a first region, and a second region provided to surround an outer periphery of the first region. The transistor is provided on the substrate in the first region. The insulating layer is provided above the transistor and over the first region and the second region. The first sealing portion is provided to divide the insulating layer and surround the outer periphery of the first region in the second region. The first sealing portion includes a first void.

A semiconductor device capable of suppressing an increase in chip area due to the widening of a conductor located on the topmost layer of a sealing ring is provided. The semiconductor device includes a semiconductor substrate and the sealing ring. The sealing ring is formed on a periphery of the semiconductor substrate in a plan view. The sealing ring includes a plurality of conductors stacked on each other. Each of the plurality of conductors has an inner peripheral edge and an outer peripheral edge. An inner peripheral edge of a first conductor, which is located on the topmost layer of the plurality of conductors, is positioned more inward than any of inner peripheral edges of a plurality of second conductors located below the first conductor in a plan view.

An isotope battery may include a plurality of isotope battery sheets that are stacked in a first direction, a first external electrode, and a second external electrode. Each isotope battery sheet of the plurality of isotope battery sheets includes: a substrate including a semiconductor material; and a radiation source. The radiation source may extend through at least a portion of the substrate in the first direction. The substrate includes a first region having a first conductive type and a second region having a second conductive type. The first region may be between the radiation source and the second region. The first external electrode and the second external electrode are configured to transfer electrical energy generated by the plurality of stacked isotope battery sheets to an external load. The isotope battery has the effect of generating electrical energy with a high energy density.

Barrier-free interconnects and methods of fabrication thereof are disclosed herein. An exemplary interconnect structure has a conductive line disposed over a conductive via. The conductive line has a first conductive plug disposed in a first dielectric layer, and the first conductive plug includes an electrically conductive non-metal material, such as graphite. The conductive via includes a second conductive plug disposed in a second dielectric layer, and the second conductive plug includes a metal material, such as tungsten, ruthenium, molybdenum, or combinations thereof. The first conductive plug physically contacts the second conductive plug and the second dielectric layer. The second conductive plug physically contacts the second dielectric layer. Spacers (which are insulators) may be disposed between sidewalls of the first conductive plug and the first dielectric layer. The spacers may further be disposed between the first dielectric layer and the second dielectric layer.

A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.

A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.

A semiconductor package includes a first semiconductor chip having a first surface and a second surface. First connection pads are adjacent to the first surface. A second semiconductor chip has a lower surface facing the first surface of the first semiconductor chip and includes second connection pads, Connection bumps contact the first connection pads and the second connection pads between the first semiconductor chip and the second semiconductor chip. An adhesive layer is interposed between the first semiconductor chip and the second semiconductor chip to at least partially surround the connection bumps. The adhesive layer includes a protruding portion protruding from a side surface of the second semiconductor chip. A barrier structure covers a portion of the first connection pads, partially overlapping the second semiconductor chip on the first surface, and contacting the protruding portion of the adhesive layer.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

A semiconductor device may include a semiconductor substrate, a wire placed along at least a portion of a perimeter of the semiconductor substrate, and processing circuitry connected to the wire, the processing circuitry to, based on a signal from the wire, determine whether or not the semiconductor device is damaged.

A semiconductor device may include a semiconductor substrate, a wire placed along at least a portion of a perimeter of the semiconductor substrate, and processing circuitry connected to the wire, the processing circuitry to, based on a signal from the wire, determine whether or not the semiconductor device is damaged.