The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

Cerium oxide particles for chemical mechanical polishing and a chemical mechanical polishing slurry composition comprising same are described. A combination of the characteristic cerium oxide particles with a dishing control agent leads to the provision of a chemical mechanical polishing slurry composition that suppresses dishing occurring during the polishing process while enhancing the oxide layer polishing rate, and a method for manufacturing semiconductor devices utilizing same.

A method for forming an insulating layer pattern includes providing a substrate including two or more different types of dielectric layer regions; selectively forming a blocking layer on the substrate to include a first region on which a blocking layer is formed and a second region on which no blocking layer is formed or the blocking layer is formed less than in the first region; selectively forming an insulating layer on the second region; and etching a portion of an upper portion of the insulating layer.

A method of processing a metal layer for a semiconductor structure includes performing a metal surface recovery process to remove an oxidized or nitridized layer from a surface of the metal layer and recover a metal surface of the metal layer, performing a metal passivation process to passivate the metal surface of the metal layer and form a passivation layer, and performing an encapsulation layer deposition process to deposit an encapsulation layer on the passivation layer.

A semiconductor device manufacturing method of manufacturing a semiconductor device by machining a substrate including a first surface and a second surface opposite to the first surface is provided. The semiconductor device manufacturing method including: forming a first trimmed part by performing trimming of the substrate from the first surface side; forming a second trimmed part by performing trimming of the substrate from the first surface side; forming an adhesive layer on the first surface using a spin coating method including rotating the substrate around a rotation axis; fixing the substrate to a support member via the adhesive layer; and grinding the substrate from the second surface side to decrease a dimension in a thickness direction of the substrate. The second trimmed part includes a part which is located on an inner side with respect to the first trimmed part in a radial direction from the rotation axis.

A method for producing a ferroelectric layer or antiferroelectric layer in which a layer of a paraelectric material already deposited on a surface of a substrate with a layer thickness of at least two crystallographic unit cells is introduced into an alternating electric field. The alternating electric field is repeatedly cycled between a positive electric field strength and a negative electric field strength of amplitude greater than the coercivity field strength of the material such that the layer of paraelectric material forms a polarization.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A semiconductor device manufacturing method includes forming a first film containing a first device on a first substrate, forming a second film containing a semiconductor layer on a second substrate, and changing the semiconductor layer into a porous layer. The method further includes forming a third film containing a second device on the second film, and bonding the first substrate and the second substrate to sandwich the first film, the third film, and the second film therebetween. The method further includes separating the first substrate and the second substrate from each other at a position of the second film.

A back grinding adhesive film used to protect a surface of a wafer, the back grinding adhesive film including a base material layer, and an adhesive resin layer which is formed on one surface side of the base material layer and configured with an ultraviolet curable adhesive resin material, in which, when a viscoelastic characteristic is measured after curing the ultraviolet curable adhesive resin material by irradiating with an ultraviolet ray, a storage elastic modulus at 5 C. E (5 C.) is 2.010.sup.6 to 2.010.sup.9 Pa, and a storage elastic modulus 100 C. E (100 C.) is 1.010.sup.6 to 3.010.sup.7 Pa.

A defect density calculation method according to one embodiment of the present disclosure is a method of calculating a temporal change of the defect density distribution in a semiconductor layer. The method includes calculating the temporal change of the defect density distribution on the basis of an arithmetic function using at least the activation energy of a detect included in the semiconductor layer, the processing temperature of the semiconductor layer, and the processing time of the semiconductor layer as arguments.