A method of microfabrication includes providing a substrate having an existing pattern, wherein the existing pattern comprises features formed within a base layer such that a top surface of the substrate has features uncovered and the base layer is uncovered, depositing a selective attachment agent on the substrate, wherein the selective attachment agent includes a solubility-shifting agent, depositing a first resist on the substrate, activating the solubility shifting agent such that a portion of the first resist becomes insoluble to a first developer, developing the first resist using the first developer such that a relief pattern comprising openings is formed, wherein the openings expose the features of the existing layer, and executing a selective growth process that grows a selective-deposition material on the features and within the openings of the relief pattern to provide self-aligned selective deposition features.

Provided is an apparatus for processing a substrate, which includes a chamber having a processing space in which a process of depositing a thin-film on a substrate is performed and a structure which is installed to expose at least one surface to the processing space and in which a coating layer made of a polymer forming at least one of covalent bond and double bond at an end tail is formed on the surface exposed to the processing space. Thus, the substrate processing apparatus in accordance with an exemplary embodiment may restrict or prevent particle generation and substrate pollution generation caused by a thin-film deposited in the chamber. Also, a period of cleaning the chamber and a structure or a component in the chamber may be extended. Thus, a product yield rate and an apparatus operation efficiency may improve.

A method of forming a semiconductor device includes: forming a dummy gate structure over a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack over the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings exposes first portions of the first semiconductor material and second portions of the second semiconductor material; recessing the exposed first portions of the first semiconductor material to form sidewall recesses in the first semiconductor material; lining the sidewall recesses with a first dielectric material; depositing a second dielectric material in the sidewall recesses on the first dielectric material; after depositing the second dielectric material, annealing the second dielectric material; and after the annealing, forming source/drain regions in the openings.

An electronic component carrier tape has an elongated shape, and includes a plurality of recessed pockets at equal or substantially equal intervals in a longitudinal direction and each accommodating a respective one of the plurality of electronic components. The electronic component carrier tape includes a flat plate-shaped core at one end portion in the longitudinal direction.

Information processing device that includes: an information acquisition unit that acquires reliability degradation factor state information in a chemical mechanical polishing process of a substrate performed by a substrate processing device, the reliability degradation factor state information including at least one of wear state information indicating a wear state of components of the substrate processing device and processing state information indicating a processing state during polishing; and a state prediction unit that predicts reliability information of a polishing endpoint detection function for the reliability degradation factor state information by inputting the reliability degradation factor state information acquired by the information acquisition unit into a learning model that has been trained through machine learning to learn a correlation between the reliability degradation factor state information and reliability information of the polishing endpoint detection function that indicates reliability of an endpoint detection function that detects that the chemical mechanical polishing process has reached an endpoint.

The present inventive concept relates to an atomic layer deposition (ALD) method for forming an IGZO channel layer of a transistor device the method comprising: a deposition cycle step of performing a deposition cycle for depositing an IGZO channel layer on a substrate; and a repeat step of repeatedly performing the deposition cycle step until the IGZO channel layer is formed with a predetermined thickness, wherein in the deposition cycle step, the IGZO channel layer is formed by performing an indium oxide sub-cycle for depositing indium oxide (InO), a gallium oxide sub-cycle for depositing gallium oxide (GaO), and a zinc oxide sub-cycle for depositing zinc oxide (ZnO).

The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.

A process includes acquiring temperature data indicating a temperature of a substrate placed on the substrate stage and temperature data indicating a temperature of the coolant, calculating, based on the acquired temperature data indicating the temperature of the substrate and the acquired temperature data indicating the temperature of the coolant, a thermal resistance of a heat conduction site on a heat transfer path from the substrate to the coolant, and calculating a heat flux to the substrate for each of a plurality of steps of a process recipe defining a substrate processing to be performed on the substrate. The process also includes calculating, based on the calculated thermal resistance and the calculated heat flux, an offset value to be added to a set temperature of the coolant for each of the steps.

Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

A substrate processing apparatus configured to process a combined substrate in which a first substrate and a second substrate are bonded to each other includes a holding member configured to hold the combined substrate; a removing member configured to separate at least a peripheral portion of the first substrate from the second substrate by being inserted between the first substrate and the second substrate; an elevating mechanism configured to adjust a relative height position of the removing member with respect to the holding member; and a controller configured to control an operation of the elevating mechanism. The controller controls the operation of the elevating mechanism such that the relative height position of the removing member with respect to a target insertion position of the removing member is adjusted in an entire circumference of the combined substrate.