A semiconductor package comprises a package substrate, a first semiconductor chip comprising a semiconductor substrate, a wiring structure on the semiconductor substrate, a connection pad at an uppermost part of the wiring structure, and a protective layer on a side surface of the connection pad, a crack reduction layer on the connection pad and the protective layer and a mold layer on the crack reduction layer, wherein a coefficient of thermal expansion of the crack reduction layer is lower than a coefficient of thermal expansion of the semiconductor substrate.

A three-dimensional (3D) packaging device is provided. The 3D packaging device includes an interposer substrate, and a plurality of connection structures in the interposer substrate. The plurality of connection structures are configured to transmit at least one of an electrical signal, heat, fluid, or an optical signal.

A semiconductor package includes a package substrate, a power module on a first surface of the package substrate, a connector on the first surface of the package substrate, the connector being horizontally spaced apart from the power module, a first semiconductor chip on a second surface of the package substrate opposite to the first surface, and a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip. The first semiconductor chip vertically overlaps the power module, and the first semiconductor chip is electrically connected through the package substrate to the power module.

The present disclosure relates to a microelectronics package with a stacked arrangement, which enables efficient thermal paths for both top-side cooling and bottom-side cooling, and a process for making the same. The disclosed microelectronics package includes a carrier board, a first sub-package attached to the carrier board, and a second sub-package vertically stacked with the first sub-package. Herein, each of the first sub-package and the second sub-package includes a substrate, a flip-chip die attached to the corresponding substrate, and a heat spreader attached to the corresponding substrate and completely covering and thermally connected to the corresponding flip-chip die. The second sub-package is thermally connected to the heat spreader of the first sub-package. The substrate within the second sub-package is different from and has a higher thermal conductivity than the substrate within the first sub-package, and is thermally connected to the flip-chip die of the second sub-package.

An electric apparatus includes: a first stacked body in which a first semiconductor chip having a first switch is stacked on a first mounting portion; a second stacked body in which a second semiconductor chip having a second switch is stacked on a second mounting portion; a temperature sensor provided in the first stacked body to detect a temperature of the first switch; and a current sensor provided in the second stacked body to detect a current flowing through the second switch. The second stacked body has a heat dissipation property higher than that of the first stacked body.

A semiconductor package may include a lower semiconductor chip, a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, non-conductive layers between the lower semiconductor chip and a lowermost one of the semiconductor chips and between the semiconductor chips, a mold layer on the semiconductor chips and the non-conductive layers, and a vision layer on the mold layer. The vision layer may include a metallic material, and a bottom surface of the vision layer may be in contact with a top surface of the uppermost one of the semiconductor chips and a top surface of the mold layer.

A chip package includes a substrate, a chip and a heat dissipation sheet. The substrate includes a carrier, a circuit layer and a solder resist layer. The circuit layer is provided on the carrier, covered by the solder resist layer and has circuit lines. The solder resist layer includes a first opening, a second opening and a covering portion located between the first and second openings. Each of the circuit line has an inner lead, a first conductive section and a second conductive section. The inner lead is visible from the first opening and electrically connected to the chip, the first conductive section is covered by the covering portion, and the second conductive section is visible from the second opening. The heat dissipation sheet is adhered to the second conductive section via an electrically insulative adhesive. Thus, thermal conductivity performance and flexibility of the chip package can be improved.

The present disclosure relates to a radio frequency (RF) package with air cavities for wide bandgap semiconductors and double-sided cooling, and a process for making the same. The disclosed RF package includes a carrier board, an electrical module with a module substrate over the carrier board, an interposer over the module substrate, a flip-chip die, a heat spreader, a mold compound, a shielding structure covering the electrical module to provide a shielded module, and a heat sink over the shielded module. Herein, the flip-chip die is attached to the interposer, and the heat spreader is attached to the interposer to provide an air-cavity, within which the flip-chip die is located. The interposer, the flip-chip die, and the heat spreader are thermally coupled with each other. The mold compound resides over the module substrate and surrounds the interposer and the heat spreader without being in contact with the flip-chip die.

A semiconductor device includes an emitter electrode, a temperature sensing unit provided adjacent to the emitter electrode, a sense wiring, and a first wire bond portion provided adjacent to a connection portion between the emitter electrode and the sense wiring. The sense wiring includes a first sense wiring portion, a second sense wiring portion, and a bent portion. A distance from the connection portion to the first wire bond portion is shorter than a distance from the bent portion to the connection portion.

To provide a semiconductor device that includes: a semiconductor substrate provided with a semiconductor portion that is at least one of a gate insulating film, a pn junction, or a drift layer of a terminal region; an insulating film provided on the semiconductor portion; a metal electrode having an opening that overlaps the semiconductor portion in plan view and is provided on a side opposite to the semiconductor portion with respect to the insulating film in cross-sectional view; and a plated electrode provided at at least a portion of an inside of the opening using the metal electrode as a material to be plated.