Provided is a semiconductor package including a package substrate, a stacked structure mounted on the package substrate, and a heat dissipation structure mounted on the stacked structure, wherein the stacked structure includes a lower die, a passive device chip, a second upper die arranged apart from the passive device chip on the lower die, and a first upper die mounted on the passive device chip, and wherein the lower die includes a voltage control chip, the passive device chip includes a capacitor, and the package substrate includes an inductor.

A wafer-level cavity package with backside termination is disclosed. In one aspect, a package includes an air cavity that is adjacent to a substrate. Input/output (I/O) vias extend from the circuits in the air cavity through the substrate for connection to external pads for the package. A cap covers the air cavity and does not include metal conductors therethrough. By routing the vias through the substrate instead of the cap, numerous advantages are realized, including better thermal pathing, improved structural integrity of the cap, reductions in die and module stress, tighter frequency variation, enhanced yield, and options for shrinking overall package geometry.

A semiconductor module may include a first substrate having a first substrate surface that includes an area, a first semiconductor die disposed within the area on the first substrate surface, and a second semiconductor die disposed within the area on the first substrate surface. The semiconductor module may further include a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, with the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface that is outside of the area.

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a first power module, the first power module including: a first substrate including a first conductive layer; a second substrate including a second conductive layer; a power switch between the first conductive layer and the second conductive layer, the power switch including a gate connection, wherein the power switch is configured to selectively electrically connect the first conductive layer to the second conductive layer based on a signal to the gate connection; and a point-of-use controller between the first conductive layer and the second conductive layer, the point-of-use controller configured to provide the signal to the gate connection to control the power switch.

A method and an electronic device monitors the temperature of power electronics having at least one power transistor. In the method, during active operation of the power transistor, the drain-source voltage and the drain current of the transistor are measured and are used to calculate an on-state resistance. An instantaneous junction temperature of the power transistor is determined for monitoring the temperature on the basis of a predefined assignment. The predefined assignment is automatically recalibrated for future operation of the power transistor by automatically measuring in each case a pair of values of the instantaneous on-state resistance and an instantaneous temperature of the power electronics in each case at a plurality of different times outside active operation. These temperatures are measured at a location spatially spaced apart from the junction of the power transistor and are assumed to be junction temperatures prevailing at the respective time. The assignment is then updated according to these pairs of values.

A method and an electronic device monitors the temperature of power electronics having at least one power transistor. In the method, during active operation of the power transistor, the drain-source voltage and the drain current of the transistor are measured and are used to calculate an on-state resistance. An instantaneous junction temperature of the power transistor is determined for monitoring the temperature on the basis of a predefined assignment. The predefined assignment is automatically recalibrated for future operation of the power transistor by automatically measuring in each case a pair of values of the instantaneous on-state resistance and an instantaneous temperature of the power electronics in each case at a plurality of different times outside active operation. These temperatures are measured at a location spatially spaced apart from the junction of the power transistor and are assumed to be junction temperatures prevailing at the respective time. The assignment is then updated according to these pairs of values.

A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.

A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.