A method of processing a wafer includes forming a bonded wafer assembly by bonding one of opposite surfaces of a first wafer to a second wafer, the first wafer having a device region and an outer circumferential excessive region, applying a laser beam to the first wafer while positioning a focused spot of the laser beam radially inwardly from the outer circumferential edge of the first wafer, on an inclined plane that is progressively closer to the one of the opposite surfaces of the first wafer toward the outer circumferential edge, thereby forming a separation layer shaped as a side surface of a truncated cone, grinding the first wafer from the other one of the opposite surfaces thereof to thin down the first wafer to a predetermined thickness, and detecting whether or not the outer circumferential excessive region has been removed from the first wafer.

A method of processing a wafer includes forming a bonded wafer assembly by bonding one of opposite surfaces of a first wafer to a second wafer, the first wafer having a device region and an outer circumferential excessive region, applying a laser beam to the first wafer while positioning a focused spot of the laser beam radially inwardly from the outer circumferential edge of the first wafer, on an inclined plane that is progressively closer to the one of the opposite surfaces of the first wafer toward the outer circumferential edge, thereby forming a separation layer shaped as a side surface of a truncated cone, grinding the first wafer from the other one of the opposite surfaces thereof to thin down the first wafer to a predetermined thickness, and detecting whether or not the outer circumferential excessive region has been removed from the first wafer.

A semiconductor device includes a die and a coreless embedded trace substrate (ETS). The die has an embedded circuit. The die can include ports on a surface of the die coupled to the embedded circuit of the die. The coreless ETS can underlie the die. The ETS can include a cavity having circuit components embedded in the cavity, ports on a surface of the ETS coupled to the circuit components embedded in the cavity and solder balls coupling the ports of the ETS to the ports of the die. In some examples, the embedded circuit in the die is a switching power field effect transistor (FET), in other examples, a bulk acoustic wave (BAW) resonator. The circuits embedded in the cavity, in some instances, include a radio frequency (RF) network for the BAW resonator, in other examples, include passive circuit components.

A conveyance device includes: a container that contains a processing target; a conveyor that conveys the processing target along a predetermined conveyance path between the container and a processor that processes the processing target; an ionizer that ejects neutralization air toward the processing target conveyed by the conveyor; and a controller that controls the conveyor.

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A pH-adjusted water production device has a configuration in which a platinum group metal support resin column, a membrane-type degassing device, and a gas dissolving membrane device are provided on an ultra-pure water supply line, and a pH-adjuster injection device is provided between the platinum group metal support resin column and the membrane-type degassing device. An inert gas source is connected to the gas phase side of the membrane-type degassing device while an inert gas source is connected also on the gas phase side of the gas dissolving membrane device, and a discharge line communicates with the gas dissolving membrane device.

A peeling method of the present invention includes: a laser processing step of forming a processing layer in an SiCN film by applying, to a bonded wafer which includes a first wafer and a second wafer and in which a surface of the first wafer in which a first device and a first bonding film are formed on the surface is bonded to a surface of the second wafer in which a second bonding film including the SiCN film is formed on the surface via the first bonding film and the second bonding film, laser light having a wavelength transmissive to the second wafer from the second wafer side; and a peeling step of peeling the second wafer from the bonded wafer at the processing layer.