Embodiments provide a semiconductor device and a fabrication method. The fabrication method includes: providing a substrate including an alignment region and a connection region; forming a first conductive layer on the substrate; forming a spacer material layer group on the first conductive layer; forming a protective layer on the spacer material layer group, the protective layer being positioned on the alignment region; etching the spacer material layer group and the protective layer, an etching rate of the protective layer being less than an etching rate of the spacer material layer group to remove the spacer material layer group on the connection region to form a spacer layer group, and forming an alignment groove on the spacer layer group in the alignment region; and forming a second conductive layer group on the spacer layer group and the first conductive layer, the second conductive layer group covering the alignment groove.

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

Provided is a method of manufacturing a substrate including an alignment mark, including: forming the alignment mark and a recess portion on the substrate, the alignment mark not penetrating the substrate and including a bottom portion with a lower infrared transmittance than that of a first surface and a second surface of the substrate; and aligning the substrate by orthogonally arranging predetermined positions of the first surface and the second surface of the substrate in a horizontal direction and an infrared ray camera and by image-identifying the alignment mark formed on the substrate with transmitted light of infrared rays emitted from the infrared ray camera.

Provided is a method of manufacturing a substrate including an alignment mark, including: forming the alignment mark and a recess portion on the substrate, the alignment mark not penetrating the substrate and including a bottom portion with a lower infrared transmittance than that of a first surface and a second surface of the substrate; and aligning the substrate by orthogonally arranging predetermined positions of the first surface and the second surface of the substrate in a horizontal direction and an infrared ray camera and by image-identifying the alignment mark formed on the substrate with transmitted light of infrared rays emitted from the infrared ray camera.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first pattern and a second pattern. The first pattern is disposed on the substrate. The first pattern includes a first segment and a second segment, each of which extends along a first direction. The second pattern is disposed on the first pattern. The second pattern includes a first part extending along a second direction different from the first direction. The first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. The first pattern and the second pattern are associated with an overlay error.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first pattern and a second pattern. The first pattern is disposed on the substrate. The first pattern includes a first segment and a second segment, each of which extends along a first direction. The second pattern is disposed on the first pattern. The second pattern includes a first part extending along a second direction different from the first direction. The first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. The first pattern and the second pattern are associated with an overlay error.

A semiconductor package includes a redistribution structure including a first redistribution layer, a semiconductor chip on the redistribution structure and having a contact pad electrically connected to the first redistribution layer, a vertical connection conductor on the redistribution structure and electrically connected to the first redistribution layer, a molding portion disposed on the redistribution structure, a second redistribution layer disposed on the molding portion, connected to the vertical connection conductor, and having a plurality of first pads, each of the plurality of first pads having an alignment hole, a plurality of second pads respectively disposed on the plurality of first pads and having a side portion covering an inner sidewall of the alignment hole, the alignment hole having an inner space surrounded by the side portion, and a protective insulating layer covering the second redistribution layer, and having a plurality of contact openings respectively exposing the plurality of second pads.

A semiconductor package includes a redistribution structure including a first redistribution layer, a semiconductor chip on the redistribution structure and having a contact pad electrically connected to the first redistribution layer, a vertical connection conductor on the redistribution structure and electrically connected to the first redistribution layer, a molding portion disposed on the redistribution structure, a second redistribution layer disposed on the molding portion, connected to the vertical connection conductor, and having a plurality of first pads, each of the plurality of first pads having an alignment hole, a plurality of second pads respectively disposed on the plurality of first pads and having a side portion covering an inner sidewall of the alignment hole, the alignment hole having an inner space surrounded by the side portion, and a protective insulating layer covering the second redistribution layer, and having a plurality of contact openings respectively exposing the plurality of second pads.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.