A method for manufacturing a semiconductor structure includes forming a plurality of semiconductor stack portions spaced apart from each other by a plurality of recesses, each of which includes two sacrificial layer portions and a channel layer portion disposed therebetween, in which the channel layer portion has a plurality of crystal planes and is formed with a first straight lateral surface which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the recesses; and laterally etching the channel layer portion using the etchant to permit the channel layer portion to be formed with a second straight lateral surface.

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

A memory device may include a substrate, a lower electrode disposed on the substrate in a chip region, an upper electrode on the lower electrode, a dielectric layer disposed between the lower electrode and the upper electrode, a dummy upper electrode disposed over the substrate in a scribe lane region continuous with the chip region, and disposed at a level higher than an upper surface of the lower electrode, and an alignment key disposed on the dummy upper electrode.

A wafer map generation device includes a dimension reducer and a map generator. The dimension reducer is configured to receive a plurality of polarization matrices associated with a plurality of target positions of a target wafer substrate and to generate a plurality of reduction result data through dimension reduction of one or more elements of each of the plurality of polarization matrices. The map generator is configured to generate a wafer map associated with the target wafer substrate based on the plurality of reduction result data.

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

The invention provides an overlay mark, which comprises four sub-overlay marks, which together form an overlay mark, wherein each sub-overlay mark comprises a substrate and defines an inner region and an outer region, a plurality of first mandrel structures located in the inner region and a plurality of second mandrel structures located in the outer region, wherein the first mandrel structures are arranged in parallel with each other, and the second mandrel structures are also arranged in parallel with each other, and a plurality of strip-shaped mask layers are located in the inner region, wherein both sides of any first mandrel structure comprise a strip-shaped mask layer respectively. In addition, the invention also provides an overlay method of the semiconductor structure using the overlay mark.

Aspects of the present disclosure provide an inspection system, which can include an image module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam, and image a first pattern located on a front side of a wafer to form a first image. The second light beam can image a second pattern located below the first pattern to form a second image via quantum tunneling imaging or infrared transmission imaging. The second light beam can have power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate an overlay value of the first and second patterns and/or defects of the wafer.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

A die alignment method includes vertically aligning a first die comprising first magnetic patterns and a second die comprising second magnetic patterns with each other using magnetic force between the first magnetic patterns and the second magnetic patterns. Each of the first magnetic patterns and the second magnetic patterns comprises a horizontally magnetically anisotropic material. The first magnetic patterns and the second magnetic patterns do not vertically overlap each other when the first die and the second die are vertically aligned with each other.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.