An integrated sensor component includes a chip carrier and a first semiconductor chip and a second semiconductor chip, wherein either both semiconductor chips are arranged on the chip carrier or (alternatively) the second semiconductor chip is arranged on the chip carrier and the first semiconductor chip is arranged on the second semiconductor chip (chip-on-chip). The integrated sensor component further includes a first sensor element integrated in the first semiconductor chip and a second sensor element integrated in the second semiconductor chip, as well as a housing formed by a potting compound, which has an opening. Both the first sensor element and the second sensor element are located within the opening so that they can interact with the atmosphere surrounding the sensor component.

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

The present disclosure provides a method for manufacturing a semiconductor package. The method includes disposing a first semiconductor substrate on a temporary carrier and dicing the first semiconductor substrate to form a plurality of dies. Each of the plurality of dies has an active surface and a backside surface opposite to the active surface. The backside surface is in contact with the temporary carrier and the active surface faces downward. The method also includes transferring one of the plurality of dies from the temporary carrier to a temporary holder. The temporary holder only contacts a periphery portion of the active surface of the one of the plurality of dies.

A system and method of improving electromagnetic compatibility robustness of die-to-die interconnects within MDMs operating in environments susceptible to EMI. The method includes providing a package substrate. The method includes disposing a first integrated circuit (IC) die on a top side of the package substrate. The method includes disposing a second IC on the top side of the package substrate. The method includes enclosing the first IC die and the second IC die with a molding component. The method includes embedding a communication bus within the package substrate and electrically coupling the communication bus between the first IC die and the second IC die. The method includes configuring the package substrate to attenuate EMI incident upon at least one of the first IC die or the second IC die, to reduce or prevent the EMI from coupling into the communication bus.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

Embodiments herein describe techniques for an IC package including a supporting layer having a first zone and a second zone. An electronic component is placed above the first zone of the supporting layer. An underfill material is formed above the first zone of the supporting layer, around or below the electronic component to support the electronic component. The second zone of the supporting layer includes a base area and multiple micro-pillars above the base area, where any two micro-pillars of the multiple micro-pillars are separated by a gap in between. The second zone has a hydrophobic surface including surfaces of the multiple micro-pillars and surfaces of the base area. The second zone is a keep out zone to prevent the underfill material from entering the second zone. Other embodiments may be described and/or claimed.

In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

An apparatus for producing a semiconductor device comprises a stage, a bonding head, a bonding tool and a first camera that are attached to the bonding head, and a controller, the apparatus moreover being such that the controller is configured to execute for each of one or more points: a process of mounting an inspection chip on a mounting surface; a process of acquiring, as an inspection image, an image of the mounting surface after the inspection chip has been mounted thereon captured by the first camera; a process of calculating, as an area correction amount C, a correction amount for a camera offset amount Ocm on the basis of the position of the inspection chip in the inspection image; and a process of associating the calculated area correction amount C and the position of a discretionary point and then storing the associated information in a storage device.

The present invention provides an integrated circuit package capable of independently assembling passive devices and a manufacturing method thereof. The integrated circuit package includes: an integrated circuit configured to be mounted on a circuit board; and a heat dissipation structure, which is manufactured independently and has a first-layer flat plate disposed above the integrated circuit and in thermal contact therewith, and a cavity located on one side of the first-layer flat plate. The cavity is formed with at least one opening to accommodate a passive device. During assembly, the passive device is inserted into the cavity of the heat dissipation structure through the at least one opening and is electrically connected to the circuit board or the integrated circuit via an electrical conductor of the passive device. Heat generated by the integrated circuit is transferred through the heat dissipation structure.

Provided are a highly reliable electromagnetic wave shielding sheet that is capable of performing batch coating on a wafer before dicing and has excellent coating properties, a shielded wafer formed using the electromagnetic wave shielding sheet, a semiconductor device, and a manufacturing method thereof. An electromagnetic wave shielding sheet 3 for performing batch coating on a semiconductor wafer before dicing includes at least a shielding film 30 including a conductive filler (F) and a binder component, has an elongation rate of 100% to 1500% at 100 C., and has a Young's modulus of 100 MPa to 1000 MPa at 100 C. in a cured sheet after treating the electromagnetic wave shielding sheet 3 at 180 C. for 2 hours.