A high-voltage device includes a substrate, a gate structure over the substrate, a drain region disposed on a first side of the gate structure, a plurality of source regions disposed on a second side of the gate structure, and a plurality of doped regions disposed on the second side of the gate structure. The gate structure includes a plurality of first portions and a plurality of second portions alternately arranged. Width of the first portions are greater than widths of the second portions. The source regions are adjacent to the first portions of the gate structures, and the doped regions are adjacent to the second portions of the gate structure. The drain region and the source regions include dopants of a first conductivity type, and the doped regions include dopants of a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source/drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source/drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source/drain regions into a plurality of germanium condensed portions.