The present disclosure provides an article having a substrate having a first nanostructured surface and an opposing second surface; and a conductor micropattern disposed on the first surface of the substrate, the conductor micropattern formed by a plurality of traces. The micropattern may have an open area fraction greater than 80%. The traces of the conductor micropattern may have a specular reflectance in a direction orthogonal to and toward the first surface of the substrate of less than 50%. The nanostructured surface may include nanofeatures having a height from 50 to 750 nanometers, a width from 15 to 200 nanometers, and a lateral spacing from 5 to 500 nanometers. The articles are useful in devices such as displays, in particular, touch screen displays useful for mobile hand held devices, tablets and computers. They also find use in antennas and for EMI shields.

Various examples related to fabrication of thermally stable ultra-high density particle-in-cavity (PIC) nanostructures. In one example, a method includes disposing an anodized aluminum oxide (AAO) template onto a surface of a substrate; removing, from the AAO template, a support layer disposed on a side of the AAO template opposite the surface of the substrate; etching nanocavities into the surface of the substrate using the AAO template as an etch mask; and removing the AAO template from the surface of the substrate. The method can include fabricating the AAO template on an aluminum substrate by anodization of an aluminum film and removing the AAO template from the aluminum substrate after formation of the support layer on the AAO template.

A mesoporous, nanocrystalline, metal oxide construct particularly suited for capacitive energy storage that has an architecture with short diffusion path lengths and large surface areas and a method for production are provided. Energy density is substantially increased without compromising the capacitive charge storage kinetics and electrode demonstrates long term cycling stability. Charge storage devices with electrodes using the construct can use three different charge storage mechanisms immersed in an electrolyte: (1) cations can be stored in a thin double layer at the electrode/electrolyte interface (non-faradaic mechanism); (2) cations can interact with the bulk of an electroactive material which then undergoes a redox reaction or phase change, as in conventional batteries (faradaic mechanism); or (3) cations can electrochemically adsorb onto the surface of a material through charge transfer processes (faradaic mechanism).

The disclosure relates to an epitaxial structure. The epitaxial structure includes a substrate, an epitaxial layer, and a nanotube film. The substrate has an epitaxial growth surface. The epitaxial layer is located on the epitaxial growth surface of the substrate. The nanotube film is located between the substrate and the epitaxial layer. The nanotube film includes a number of nanotubes orderly arranged and combined with each other by ionic bonds.

The disclosure relates to an epitaxial structure. The epitaxial structure includes a substrate, an epitaxial layer, and a nanotube film. The substrate has an epitaxial growth surface. The epitaxial layer is located on the epitaxial growth surface of the substrate. The nanotube film is located between the substrate and the epitaxial layer. The nanotube film includes a number of nanotubes orderly arranged and combined with each other by ionic bonds.

The present disclosure provides an article having a conductor micropattern disposed on a major surface of a substrate. The conductor micropattern includes a plurality of curved traces defining a plurality of cells not lying on a repeating array. The conductor micropattern may have a uniform distribution of trace orientation. The conductor micropattern may be a tri-layer material including in sequence a semi-reflective metal, a transparent layer, and a reflective layer disposed on the transparent layer. The articles are useful in devices such as displays, in particular, touch screen displays useful for mobile hand held devices, tablets and computers. They also find use in antennas and for EMI shields.

A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first dopant regions on opposing sides of a channel region of the low temperature polysilicon semiconductor layer. The method may further include epitaxially forming second dopant regions on the first dopant regions. The concentration of the conductivity type dopant in the second dopant regions is greater than a concentration of the conductivity type dopant in the first dopant region. The second dopant regions are formed using a low temperature epitaxial deposition process at a temperature less than 350 C.

A fluidic processor device and a wafer including the same, the device including a nanofluidic separator chip including a nanoDLD array, a housing for housing the chip including a top plate disposed on a topside of the chip, a bottom plate disposed on a backside of the chip and fastened to the top plate, and a spacer disposed between the chip and the bottom plate to create a clearance between the chip and the bottom plate for forming a drain space on the backside of the chip.

A fluidic processor device and a wafer including the same, the device including a nanofluidic separator chip including a nanoDLD array, a housing for housing the chip including a top plate disposed on a topside of the chip, a bottom plate disposed on a backside of the chip and fastened to the top plate, and a spacer disposed between the chip and the bottom plate to create a clearance between the chip and the bottom plate for forming a drain space on the backside of the chip.

A fluidic processor device and a wafer including the same, the device including a nanofluidic separator chip including a nanoDLD array, a housing for housing the chip including a top plate disposed on a topside of the chip, a bottom plate disposed on a backside of the chip and fastened to the top plate, and a spacer disposed between the chip and the bottom plate to create a clearance between the chip and the bottom plate for forming a drain space on the backside of the chip.