An exposure mask includes a substrate, and a plurality of first films and a plurality of second films located alternately over each other over selected portions of the substrate. The exposure mask further includes a third film selectively located over the first and second films. At least one first pattern is located over the substrate and does not include any of the first, second or third films. At least one second pattern is located over the substrate and includes the first and second films and does not include the third film. At least one third pattern is located over the substrate and includes the first, second and third films.

An exposure mask includes a substrate, and a plurality of first films and a plurality of second films located alternately over each other over selected portions of the substrate. The exposure mask further includes a third film selectively located over the first and second films. At least one first pattern is located over the substrate and does not include any of the first, second or third films. At least one second pattern is located over the substrate and includes the first and second films and does not include the third film. At least one third pattern is located over the substrate and includes the first, second and third films.

The present invention relates to a liquid crystal display device that includes a particular color filter containing a material containing chiral liquid crystals and a particular pigment. The present invention provides a liquid crystal display device that can prevent a decrease in the voltage holding ratio (VHR) of a liquid crystal layer and solve the problem of display defects, such as white spots, variations in alignment, and burn-in. Because liquid crystal display devices according to the present invention characteristically prevent a decrease in the voltage holding ratio (VHR) of a liquid crystal layer and reduces the occurrence of display defects, such as burn-in, the liquid crystal display devices are particularly useful as liquid crystal display devices in IPS mode and FFS mode for active-matrix driving and can be applied to household electrical appliances, automobiles, production facilities, measuring and analytical instruments, and communication devices.

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

A method of determining the position of a first edge of a pattern in a mask used in fabricating an integrated circuit in which the first edge corresponds to a second edge associated with the pattern of a layout of the integrated circuit, includes, in part, dividing the edge into a multitude of segments, assigning a variable to each segment, applying a non-linear optimization algorithm to a current location of the first edge to determine an updated position of the first edge, determining a difference between the position of the second edge and a third edge corresponding to the updated position of the first edge and obtained by computer simulation of the mask pattern providing a model of the layout pattern when formed on a semiconductor wafer, and repeating the applying and the determining steps iteratively until the difference is smaller than a threshold value.

Provided are an array substrate and a manufacturing method therefor, a display device, and a mask plate. The array substrate includes a pixel defining layer having a first opening, a second opening, and a third opening passing through the pixel defining layer. Every two of the first to third openings are adjacent to each other. The pixel defining layer includes first to third opening denning portions. At least one of the ratio of the slope angle of a portion of the first opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion, and the ratio of the slope angle of a portion of the second opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion is from 0.8 to 1.25.

A method includes forming a photoresist layer over a wafer. The photoresist layer is exposed to a pattern of radiation using a photomask. The photoresist layer is developed after the photoresist layer is exposed to the pattern of radiation. The photomask includes a substrate and at least one opaque main feature. The substrate has a recessed region recessed from a first surface of the substrate and has a first width. The at least one opaque main feature protrudes from the first surface of the substrate and has a second width greater than the first width of the recessed region of the substrate. A height of the at least one opaque main feature is greater than a depth of the recess region of the substrate.

A method includes forming a photoresist layer over a wafer. The photoresist layer is exposed to a pattern of radiation using a photomask. The photoresist layer is developed after the photoresist layer is exposed to the pattern of radiation. The photomask includes a substrate and at least one opaque main feature. The substrate has a recessed region recessed from a first surface of the substrate and has a first width. The at least one opaque main feature protrudes from the first surface of the substrate and has a second width greater than the first width of the recessed region of the substrate. A height of the at least one opaque main feature is greater than a depth of the recess region of the substrate.