Patent classifications
G03F1/00
MASK ORIENTATION
A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.
Method of determining control parameters of a device manufacturing process
A method including: obtaining an image of at least part of a substrate, wherein the image includes at least one feature of a device being manufactured in a layer on the substrate; obtaining a layout of features associated with a previous layer adjacent to the layer on the substrate; calculating one or more image-related metrics in dependence on: 1) a contour determined from the image including the at least one feature and 2) the layout; and determining one or more control parameters of a lithographic apparatus and/or one or more further processes in a manufacturing process of the device in dependence on the one or more image-related metrics, wherein at least one of the control parameters is determined to modify the geometry of the contour in order to improve the one or more image-related metrics.
Method of determining control parameters of a device manufacturing process
A method including: obtaining an image of at least part of a substrate, wherein the image includes at least one feature of a device being manufactured in a layer on the substrate; obtaining a layout of features associated with a previous layer adjacent to the layer on the substrate; calculating one or more image-related metrics in dependence on: 1) a contour determined from the image including the at least one feature and 2) the layout; and determining one or more control parameters of a lithographic apparatus and/or one or more further processes in a manufacturing process of the device in dependence on the one or more image-related metrics, wherein at least one of the control parameters is determined to modify the geometry of the contour in order to improve the one or more image-related metrics.
Array substrate and manufacturing method therefor, display device, and mask plate
Provided are an array substrate and a manufacturing method therefor, a display device, and a mask plate. The array substrate includes a pixel defining layer having a first opening, a second opening, and a third opening passing through the pixel defining layer. Every two of the first to third openings are adjacent to each other. The pixel defining layer includes first to third opening denning portions. At least one of the ratio of the slope angle of a portion of the first opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion, and the ratio of the slope angle of a portion of the second opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion is from 0.8 to 1.25.
Array substrate and manufacturing method therefor, display device, and mask plate
Provided are an array substrate and a manufacturing method therefor, a display device, and a mask plate. The array substrate includes a pixel defining layer having a first opening, a second opening, and a third opening passing through the pixel defining layer. Every two of the first to third openings are adjacent to each other. The pixel defining layer includes first to third opening denning portions. At least one of the ratio of the slope angle of a portion of the first opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion, and the ratio of the slope angle of a portion of the second opening defining portion located between the first opening and the second opening to the slope angle of the third opening defining portion is from 0.8 to 1.25.
DISPLAY PANEL AND MASK PLATE FOR FABRICATING THE SAME
A display panel and a mask plate for fabricating the display panel are provided. The mask plate is configured to fabricate the display panel, and includes a display region, provided with a number of first through holes arranged at intervals; and a transition display region, disposed at a periphery of the display region, and provided with a number of second through holes arranged at intervals. A density of the second through holes is smaller than a density of the first through holes. The present application further relates to a display panel. The display panel includes a display substrate and pixels arranged in an array on the display substrate. The pixels are fabricated from the mask plate as described above.
Mask orientation
A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.
Mask plate, manufacturing method of patterned film layer and manufacturing method of thin film transistor
A mask plate, a method for manufacturing a patterned film layer and a manufacturing method of a thin film transistor are provided by the embodiments of the present disclosure. The mask plate includes: a first pattern and a second pattern; the first pattern includes a first sidewall, a second sidewall, a connecting portion connecting the first sidewall and the second sidewall, and an extension portion on a side of the connecting portion away from the first sidewall; the second pattern is between the first sidewall and the second sidewall; a slit is between the first pattern and the second pattern, and the slit is configured for diffraction. The positive photoresist is used, the extension portion of the mask plate makes that the pattern of the photoresist formed by the mask plate with the extension portion has a region corresponding to the extension portion and the “bolt effect” is avoided.
METHOD FOR CREATION OF DIFFERENT DESIGNS BY COMBINING A SET OF PRE-DEFINED DISJOINT MASKS
Described are methods for enabling the creation of multiple similar designs by utilizing sets of multiple, disjoint fabrication masks. A first set of device features may be formed from a material layer in a first portion of a die area of a semiconductor substrate based on a first photolithographic exposure. A second set of device features may be formed from the material layer in a second portion of the die area of the semiconductor substrate based on a second photolithographic exposure after the first photolithographic exposure. The first portion of the die area and the second portion of the die area may be non-overlapping.
MANUFACTURING METHOD OF THIN FILM TRANSISTOR PATTERN, THIN FILM TRANSISTOR, AND MASK
The present disclosure provides a manufacturing method of a TFT pattern, and a mask, which is used to make light pass through a hole corresponding to a position of the TFTs on the mask which is disposed on the TFTs, thereby producing two or more stacked photoresists on the TFTs to counteract a reflected light on a semiconductor As layer and ensure normal working of the TFTs.