The present disclosure provides a manufacturing method of a TFT pattern, and a mask, which is used to make light pass through a hole corresponding to a position of the TFTs on the mask which is disposed on the TFTs, thereby producing two or more stacked photoresists on the TFTs to counteract a reflected light on a semiconductor As layer and ensure normal working of the TFTs.

A mask is provided. The mask includes a plurality of light blocking strips configured to block light and bounding spaces through which light is allowed to pass. The plurality of light blocking strips are arranged in a mesh shape, and include first light blocking strips located in at least one side edge of the mask, and second light blocking strips, and each of the first light blocking strips has a greater width than each of the second light blocking strips. An exposure method using the mask, and a touch display panel manufactured by the exposure method are also provided.

A simulation apparatus includes: a factor amount converting information storage unit in which factor amount converting information, which is information indicating correspondence between low-fidelity information and high-fidelity information, is stored; a writing pattern information storage unit in which writing pattern information is stored; an ADI simulation unit that performs an ADI simulation using one or more evaluation points, for a writing pattern indicated by the writing pattern information, thereby acquiring one or more factor amounts; a converting unit that acquires high-fidelity information, which is one or more factor amounts, corresponding to the low-fidelity information, which is one or more factor amounts, using the factor amount converting information; and an etching simulation unit that performs an etching simulation using the one or more factor amounts acquired by the converting unit.

A simulation apparatus includes: a factor amount converting information storage unit in which factor amount converting information, which is information indicating correspondence between low-fidelity information and high-fidelity information, is stored; a writing pattern information storage unit in which writing pattern information is stored; an ADI simulation unit that performs an ADI simulation using one or more evaluation points, for a writing pattern indicated by the writing pattern information, thereby acquiring one or more factor amounts; a converting unit that acquires high-fidelity information, which is one or more factor amounts, corresponding to the low-fidelity information, which is one or more factor amounts, using the factor amount converting information; and an etching simulation unit that performs an etching simulation using the one or more factor amounts acquired by the converting unit.

A display device includes: a first substrate including a display area and a non-display area including a first non-display area and a second non-display area on respective sides of the display area with respect to a first direction; a color filter in the display area and including a first color filter, a second color filter, and a third color filter; and a color filter dam in the non-display area, wherein the color filter dam includes a first color filter dam in the first non-display area and a second color filter dam in the second non-display area, the first color filter dam includes a same material as the first color filter, and the second color filter dam includes a same material as the second color filter.

The method includes the steps of: a) dividing a large-scale touch sensing pattern to be manufactured into multiple divisional patterns and producing multiple photomasks corresponding to the multiple divisional patterns; b) providing a substrate with a conductive layer; c) disposing a photoresist layer on the conductive layer; d) a first exposure process: forming an exposing divisional pattern and multiple first targets the photoresist layer; e) an adjacent exposure process: forming an adjacent exposing divisional pattern and multiple second targets, and adjacently connecting the adjacent exposing divisional pattern and the exposing divisional pattern originally on the photoresist layer; f) repeating the adjacent exposure process to form multiple adjacent exposing divisional patterns until a complete exposing pattern has been assembled; g) performing a developing process to the photoresist layer; and h) etching the conductive layer to form the large-scale touch sensing pattern on the conductive layer.

In an embodiment, a method includes: receiving data representative of an electrical circuit including an arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, where N is equal to the minimum number of segments; and generating discrete portions of the grouped devices to form a physical layout representative of a physical manifestation of the electrical circuit, such that when the discrete portions are integrated together they form a physical manifestation of the electrical circuit.

A display panel and a manufacturing method thereof are disclosed. The display panel has a display area and a peripheral area, including: an array substrate, an opposite substrate, and a sealant layer including a first edge close to the display area and a second edge away from the display area. The array substrate includes a base substrate, a driving circuit and an organic insulating layer including a first part and a second part. In a direction perpendicular to a substrate surface, the first part overlaps with the sealant layer, and the second part has no overlap. In a direction parallel to the substrate surface, an edge of the first part away from the display area is between the first edge and the second edge. The driving circuit includes a gate scan driving circuit at least partially overlapped with the first part in the direction perpendicular to the substrate surface.

Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

Provided is a mask plate assembly. The mask plate assembly includes: a frame, wherein an opening portion is defined in a center portion of the frame; a shielding strip, wherein the shielding strip is disposed on the opening portion, and two ends of the shielding strip are fixed on the frame; and a mask plate, wherein the mask plate is fixed on the frame, and an evaporation hold and an elongated hole are defined in the mask plate, wherein the evaporation hole is opposite to the opening portion, and the elongated hole is opposite to the shielding strip to shield the elongated hole by the shielding strip.