A wireless communication device, including a radiofrequency frontend, configured to wirelessly receive a radiofrequency signal; perform one or more analog baseband operations on the received radiofrequency signal, according to a radio access technology; and output an analog signal representing an output of the analog baseband operations on the received radiofrequency signal; an error corrector, configured to perform an error correction operation on the analog signal; and output an error corrected signal in analog domain; and the analog-digital converter, configured to convert the error corrected signal to digital domain.

A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.

Ultra-short pulse detection. At least some example embodiments are methods including: receiving by an antenna a series of ultra-short pulses of electromagnetic energy at a repetition frequency, the receiving creates a pulse signal; self-mixing or intermodulating the pulse signal by applying the pulse signal to a non-linear electrical device, thereby creating a modulated signal; and filtering the modulated signal to recover a filtered signal having an intermodulated frequency being the repetition frequency.

A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.

A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.

Athletic activity may be tracked while providing encouragement to perform athletic activity. For example, energy expenditure values and energy expenditure intensity values may be calculated and associated with a duration and type of activity performed by an individual. These values and other movement data may be displayed on an interface in a manner to motivate the individual and maintain the individual's interest. The interface may track one or more discrete “sessions”. The sessions may be associated with energy expenditure values during a duration that is within a second duration, such as a day, that is also tracked with respect to variables, such as energy expenditure. Other individuals (e.g., friends) may also be displayed on an interface through which a user's progress is tracked. This may allow the user to also view the other individuals' progress toward completing an activity goal and/or challenge.

Athletic activity may be tracked while providing encouragement to perform athletic activity. For example, energy expenditure values and energy expenditure intensity values may be calculated and associated with a duration and type of activity performed by an individual. These values and other movement data may be displayed on an interface in a manner to motivate the individual and maintain the individual's interest. The interface may track one or more discrete “sessions”. The sessions may be associated with energy expenditure values during a duration that is within a second duration, such as a day, that is also tracked with respect to variables, such as energy expenditure. Other individuals (e.g., friends) may also be displayed on an interface through which a user's progress is tracked. This may allow the user to also view the other individuals' progress toward completing an activity goal and/or challenge.

A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109) with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner (130) is configured to provide the digitally represented output signal (139) based on the digitally represented constituent output signals (131, 132, 133) of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.