A calibration unit and method therein for calibrating a TDC comprised in a digital PLL are disclosed. The TDC receives a signal from a free-running DCO and a reference signal, and measures the time difference between the DCO and reference signals. The calibration unit receives and processes data samples output from the TDC and generates a calibration lookup table in which each TDC output value has a calibration value. The calibration lookup table may be used for post-distortion. For each TDC output level the corresponding calibration value from the lookup table may be added to the output of the TDC for correction.

An electronic device may display a first lap time representation, and may move the first lap time representation in accordance with a first amount of elapsed time. While moving the first lap time representation, the electronic device may detect a lap input. In response to the lap input, the electronic device may cease movement of the first lap time representation, display a second lap time representation, and move the second lap time representation in accordance with a second amount of elapsed time. A relative positioning of the first lap time representation and the second lap time representation may correspond to a difference between a first lap time and a second lap time. In some embodiments, the electronic device may update the timescales of lap time representation(s) in accordance with a rotational input. In some embodiments, the electronic device may update a timer duration setting in accordance with a rotational input.

An electronic device may display a first lap time representation, and may move the first lap time representation in accordance with a first amount of elapsed time. While moving the first lap time representation, the electronic device may detect a lap input. In response to the lap input, the electronic device may cease movement of the first lap time representation, display a second lap time representation, and move the second lap time representation in accordance with a second amount of elapsed time. A relative positioning of the first lap time representation and the second lap time representation may correspond to a difference between a first lap time and a second lap time. In some embodiments, the electronic device may update the timescales of lap time representation(s) in accordance with a rotational input. In some embodiments, the electronic device may update a timer duration setting in accordance with a rotational input.

Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (S.sub.A, S.sub.B, S.sub.C, S.sub.D), the number of the interim signals corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (S.sub.A, S.sub.B, S.sub.C, S.sub.D) and a reference voltage corresponding to a particular preset voltage threshold (V.sub.A, V.sub.B, V.sub.C, V.sub.D); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences (20A, 20B, 20C, 20D) and connected to a common clock signal (CLK), current values of output signals of each of the delay elements (21, 22, 23) in the particular sequence (20A, 20B, 20C, 20D) at the same moment for all vector generators and providing these values as sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D); and determining times at which the analog signal (S) crosses the predetermined voltage thresholds (V.sub.A, V.sub.B, V.sub.C, V.sub.D) on the basis of the values of the sequence output vectors (W.sub.A, W.sub.B, W.sub.C, W.sub.D) and the delays introduced by the delay elements (21, 22, 23).

A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.

An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.

A time-to-digital converter includes a self-calibrating, n-stage chain of a number n of gate delay elements connected in parallel and series between a clock signal line for supplying a clock signal and a stop signal line for supplying a stop signal; and a charge-pump and phase-detector unit for the feedback control of the gate delay elements, having a first input as a controlled-variable input, a second input as a reference-variable input, and an output as a correcting-variable output. The clock signal line is connected to the first input of the charge-pump and phase-detector unit, a push-pull line for supplying a push-pull signal is connected to the second input, and, for feedback, the gate delay elements are connected to the output of the charge-pump and phase-detector unit.