A time-passage indicator device can comprise a housing, a plurality of light elements located inside the housing, a window comprising an inner and an outer surface, and a processor that controls the plurality of light elements. Some devices also contain a touch sensor, and the processor controls the light elements based upon signals from the touch sensor. The window can be attached to the housing and diffuses or scatters the light from the plurality of light elements. The light elements can emit light through the window forming an illuminated region viewable by a user. The processor can control the light elements such that the illuminated region changes to indicate the passage of time. The illuminated region can be viewable from all angles between 10 degrees and 90 degrees, where the angle of 90 degrees corresponds to a normal viewing angle.

A time-passage indicator device can comprise a housing, a plurality of light elements located inside the housing, a window comprising an inner and an outer surface, and a processor that controls the plurality of light elements. Some devices also contain a touch sensor, and the processor controls the light elements based upon signals from the touch sensor. The window can be attached to the housing and diffuses or scatters the light from the plurality of light elements. The light elements can emit light through the window forming an illuminated region viewable by a user. The processor can control the light elements such that the illuminated region changes to indicate the passage of time. The illuminated region can be viewable from all angles between 10 degrees and 90 degrees, where the angle of 90 degrees corresponds to a normal viewing angle.

A controller includes a phase frequency detection circuit which has a first input coupled to receive a reference clock input, a second input coupled to receive a high-side active output, and an output configured to provide a PFD output. The controller includes a control loop filter which has a first input coupled to receive a slew rate input, a second input coupled to receive the PFD output, and an output configured to provide a high-side length output. The controller includes a pulse generation circuit which has a first input coupled to receive the high-side active output, a second input coupled to receive the high-side length output, and an output configured to provide a fine pulse output. The controller includes a latch configured to provide the high-side active output responsive to a comparison output and the fine pulse output.

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

An N-element baseband (BB) time-domain spatial signal processor system and methodology for large modulated bandwidth multi-antenna receivers are provided. Such a processor generally includes a pipeline converter configured as an asynchronous time-to-digital converter, wherein the asynchronous time-to-digital converter arrangement generates a residue value and an asynchronous pulse and is further arranged to amplify the residue value so as to result in an amplified residue value; and a 2-bit flash time-to-digital-converter configured to quantize the amplified residue value. Thus, a true-time delay spatial signal processing system and technique in the time-domain that enables beamforming, beam-nulling and multiple independent interference cancellation after time-alignment of signals using cascaded voltage-to-time converters and quantization using relaxed pipeline time-to-digital converters is presented.

An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.

A controller includes a phase frequency detection circuit which has a first input coupled to receive a reference clock input, a second input coupled to receive a high-side active output, and an output configured to provide a PFD output. The controller includes a control loop filter which has a first input coupled to receive a slew rate input, a second input coupled to receive the PFD output, and an output configured to provide a high-side length output. The controller includes a pulse generation circuit which has a first input coupled to receive the high-side active output, a second input coupled to receive the high-side length output, and an output configured to provide a fine pulse output. The controller includes a latch configured to provide the high-side active output responsive to a comparison output and the fine pulse output.

An apparatus and method are disclosed with some embodiments including an analog and time to digital converter (ATDC) including a receiver, the receiver for receiving an analog channel input for conversion to a digital data, the digital data having at least one bit, and a defined absolute reference time stamp, the defined absolute reference time stamp representing an absolute reference time associated with conversion of the analog channel input to the digital data and an analog-to-digital converter, the converter converting the analog channel input to the digital data.

A watch including a control member that is able to manage at least one first function of the watch and at the same time to control one or more additional electronic functions. The control member, for example a crown or a push-piece head, is mounted on the elongate element defining a central axis and passing through a wall of the watch middle. At least one strain gauge is mounted around the elongate element and arranged so as to produce an electrical signal representing a radial force exerted by the elongate element on the strain gauge when a user laterally exerts a force on the control member. A processor generates at least one command on the basis of the electrical signal, for example to enable the user to navigate in a menu or a calendar displayed on a digital screen.

A watch including a control member that is able to manage at least one first function of the watch and at the same time to control one or more additional electronic functions. The control member, for example a crown or a push-piece head, is mounted on the elongate element defining a central axis and passing through a wall of the watch middle. At least one strain gauge is mounted around the elongate element and arranged so as to produce an electrical signal representing a radial force exerted by the elongate element on the strain gauge when a user laterally exerts a force on the control member. A processor generates at least one command on the basis of the electrical signal, for example to enable the user to navigate in a menu or a calendar displayed on a digital screen.