In a power supplying system, a selection unit that selects one of a first power feed unit and a second power feed unit, a first voltage determination unit that compares a voltage of an output of the first power feed unit with a first threshold value, a second voltage determination unit that compares a voltage of an output of the second power feed unit with a second threshold value, and a management unit that sets the first threshold value and the second threshold value are provided.

A powered device interface includes a supply sensing circuit, a demand sensing circuit, and a control circuit. The supply sensing circuit is configured to sense an amount of power received by the powered device from at least one power source equipment over an ethernet cable. The demand sensing circuit is configured to sense a power demand requested by the powered device. The control circuit is coupled with the supply sensing circuit and the demand sensing circuit and is configured to cause the power demand requested by the powered device to be reduced when the power demand requested by the powered device exceeds the amount of power allowed by the power source equipment for the powered device.

A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

An integrated circuit device includes a plurality of cells or modules. Each respective one of the cells or modules consumes leakage power, and the amount of leakage power consumed by a respective one of the cells or modules varies depending on states of its inputs. Scan-chain circuitry is configured to propagate through the integrated circuit device, on entry of the integrated circuit device to a low-power mode, a scan-chain pattern created in advance, to apply, to each respective cell or module in the low-power mode, a set of inputs that results in a respective low-power state with reduced leakage power. Creating the scan chain pattern includes identifying respective ones of the cells or modules as having the highest leakage power consumption, and a respective combination of inputs to place each of those the cells or modules in a respective low-power state.

Apparatuses and methods are disclosed for managing discovery in wireless peer-to-peer networks. Various discovery procedures may be implemented by supporting a broadcast of a plurality of discovery signals spaced apart in time by silent periods from a peer node and changing the duration of at least one of the silent periods.

A thermostat may include one or more temperature sensors, a processor configured to operate in a sleep mode and a wake mode, and a Wi-Fi chip that wirelessly communicates with a thermostat management server. The Wi-Fi chip may be configured to receive data packets from the thermostat management server while the processor operates in the sleep mode, and determine a priority level of the received data packets. The priority level may include a standard priority level and a keep-alive priority level. The Wi-Fi chip may also be configured to filter the received data packets based on the determined priority level of each packet such that the keep-alive priority level packets are discarded, and forward the standard priority level packets to the processor.

A thermostat may include one or more temperature sensors, a processor configured to operate in a sleep mode and a wake mode, and a Wi-Fi chip that wirelessly communicates with a thermostat management server. The Wi-Fi chip may be configured to receive data packets from the thermostat management server while the processor operates in the sleep mode, and determine a priority level of the received data packets. The priority level may include a standard priority level and a keep-alive priority level. The Wi-Fi chip may also be configured to filter the received data packets based on the determined priority level of each packet such that the keep-alive priority level packets are discarded, and forward the standard priority level packets to the processor.

A method and system for predicting a next navigation event are described. Aspects of the disclosure minimize the delay between a navigation event and a network response by predicting the next navigation event. The system and method may then prerender content associated with the next navigation event. For example, the method and system may predict a likely next uniform resource locator during web browsing to preemptively request content from the network before the user selects the corresponding link on a web page. The methods describe a variety of manners of predicting the next navigation event, including examining individual and aggregate historical data, text entry prediction, and cursor input monitoring.

Systems and methods of enabling modulation of a frequency of a first core in a multi-core environment include logic to determine a power limit assigned to the first core, logic to determine a stall count of the first core, and logic to modulate the frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core. The first core is included in a first tile of a socket in the multi-core computer environment.