Technologies are generally described for systems, devices and methods effective to schedule access to a core. In some examples, a first differential voltage frequency scaling (DVFS) value of a first virtual machine may be received by a virtual machine manager. A second DVFS value of a second virtual machine may be received by the virtual machine manager. A third DVFS value of a third virtual machine may be received by the virtual machine manager. The third DVFS value may be substantially the same as the first DVFS value and different from the second DVFS value. A dispatch cycle may be generated to execute the first, second and third virtual machines on the core. After execution of the first virtual machine, the dispatch cycle may require execution of the third virtual machine before execution of the second virtual machine.

A power transmitting device includes a processor circuit. The processor circuit receives messages, such as advertising messages and/or scan response messages, from power receiving devices. The messages include device specific data that pertains to the corresponding power receiving devices that transmitted the messages. The device specific data includes, for example, data pertaining to the hardware, firmware, charging state, and/or device state of the corresponding power receiving device. The processor circuit selects one of the power receiving devices based in part on the device specific data contained in the messages. The processor circuit initiates a wireless power transfer connection to the selected one of the power receiving devices.

Various apparatus and methods using phase change materials are disclosed. In one aspect, a method of operating a computing device that has a first semiconductor chip with a first phase change material and a second semiconductor chip with a second phase change material is provided. The method includes determining if the first semiconductor chip phase change material has available thermal capacity. If the first semiconductor chip phase change material has available thermal capacity then the first semiconductor chip is instructed to operate in sprint mode. The first semiconductor chip is instructed to perform a first computing task while in sprint mode.

In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

A first operating condition and a second operating condition at a power supply unit (PSU) are determined at a first time. A power conversion efficiency of the PSU is determined at the first time. A first entry at a power conversion efficiency profile is generated, the first entry associating the first power conversion efficiency with the first operating condition and the second operating condition.

Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

A distributed power control system is provided. The system can include a datacenter and a remote master control system. The datacenter can include (i) computing systems, (ii) a behind-the-meter power input system configured to receive power from a behind-the-meter power source and deliver power to the computing systems, and (iii) a datacenter control system configured to control the computing systems and the behind-the-meter power input system. The remote master control system can be configured to issue instructions to the datacenter that affect an amount of behind-the-meter power consumed by the datacenter. The datacenter control system can receive, from a local station control system configured to at least partially control the behind-the-meter power source, a directive for the datacenter to ramp-down power consumption, and in response to receiving the directive, cause the computing systems to perform a set of predetermined operations correlated with the directive.

A wiring substrate includes an insulating base that has a plate surface; a first circuit that is provided on the plate surface; a first terminal that is provided on the plate surface, and to which a mounting member is attached; a second terminal that is provided on the plate surface; a first wiring that connects the first circuit and the first terminal to each other; and a second wiring that connects the first terminal and the second terminal to each other, is electrically connected to the first wiring in the first terminal, and has a parallel section in which the second wiring is disposed close to and parallel to the first wiring without being electrically connected to the first wiring outside the first terminal.

A method for managing electrical power to a server or server system is used in a power management system. The power management system comprises a power module, a backup power module, and a server system, the method comprises setting the server system to operate under a first working mode and controlling initialization of a BMC by an initialization command. A specified pin of the BMC is measured for a logic low voltage level and the server system is set to operate under a second working mode if the specified pin of the BMC is at the logic low voltage level. In different modes, the manner of supplying power and the working parameters of the server system are adjusted.

Systems and methods for dive masks with multiple interfaces in accordance with embodiments of the invention are illustrated. Dive masks include dive device data interfaces that obtain dive device data by communicating with dive devices. Dive masks can additionally include configuration interfaces that obtain configuration data through wireless communication with configuration devices. Furthermore, a dive mask can have a display processing application which can receive configuration data, receive dive device data, and display dive device data in accordance with configuration data.