A display apparatus includes a display panel and a power supply. The display panel displays an image at a first driving frequency in a normal mode and displays an image at a second driving frequency in a low power mode. The second driving frequency is lower than the first driving frequency. The power supply outputs a first initialization voltage at a first level to the display panel during an active period of the low power mode. The power supply outputs a second initialization voltage at a second level to the display panel during at least a portion of a blank period of the low power mode. The second level is higher than the first level.

An information processing apparatus includes: a main control unit that executes processing based on an operating system (OS) and that changes to a low power consumption mode to stop some functions including a display unit while making a predetermined function work; a setting information storage unit that stores a usage status mode based on usage status and setting information in association with one another, where the setting information indicates whether to stop the predetermined function implemented by a device driver added to the OS in the low power consumption mode; a mode control unit that changes the main control unit to the low power consumption mode; and a change processing unit that changes a stopped state of the predetermined function.

A chip includes an instruction storage unit, a processor core, an input circuit, a neural network circuit, power-consuming circuits, and a switch circuit. When the chip runs, the processor core performs a processing operation according to the instructions under being supplied with a current. At the same time, the neural network circuit predicts an upcoming change of the current according to data stream, representing the time-varying current, from the input circuit, and outputs a corresponding control signal. The switch circuit selectively provides a clock to one or more power-consuming circuits under the control of the control signal, so that each power-consuming circuit receiving the clock operates under being supplied with the current. Therefore, the chip can predict upcoming requirement of high electricity consumption, and duly start up a current wasting mechanism in advance, to avoid an excessive voltage drop without affecting operation efficiency of the processor core.

The present disclosure relates to a method for supplying blockchain computing power and a system thereof. The method comprises the steps of: receiving a computing power purchase request sent by a user-side terminal; generating purchase result data according to the computing power purchase request; scheduling a first blockchain server to provide users with computing service according to the purchase result data; when the first blockchain server stops serving, starting timing to obtain the target duration; judging whether the first blockchain server restarts the service when the target duration is less than the preset duration threshold, and obtaining a preset result; when the preset result is YES, improving the computing power of the first blockchain server correspondingly, so that the total service duration of the user and the actually obtained total computing power remain unchanged; when the preset result is NO, scheduling a second blockchain server to provide users with computing service. The present disclosure enables the user to obtain stable computing power.

Systems and methods may provide for assuming control over a processor in response to an operating system (OS) request to transition the processor into a sleeping state and transitioning the processor into an intermediate state that has a shorter wake latency than the sleeping state. Additionally, the processor may be maintained in the intermediate state until a wake event is detected. In one example, one or more power lowering operations may be reversed in response to the wake event.

An information processing apparatus according to the present embodiment is capable of transiting to a power saving state and retains a status of a resume requesting device before the information processing apparatus transits to the power saving state. When resuming from the power saving state, the information processing apparatus acquires a status of the resume requesting device. The information processing apparatus further determines a device to which power is supplied based on a result of comparison between the status of the resume requesting device retained and the status of the resume requesting device acquired.

A power management apparatus and a power management method are provided. The method includes the following steps. Conduct a first current path during a first period. Provide a first voltage to an operation end when the first current path conducts and a microprocessor is disabled. The first voltage is used to selectively conduct a second path during the first period. Provide a second voltage to the microprocessor when the second current path conducts. The second voltage is used to turn on the microprocessor. Provide a third voltage to the operation end by the microprocessor when the microprocessor is turned on. The third voltage is used to keep the second current path conducted.

Systems and methods of adaptive thermal control are provided for information handling system platforms that may be implemented to automate and scale fan control settings by making the fan control settings relative to a reported component thermal control parameter value from a component of an information handling system platform, such as a CPU or other heat generating component. In one example, bounds for system use of vendor or component manufacturer-reported thermal control parameter values may be set for system cooling so as to confine use of these values within information handling system platform limits characterized by a manufacturer of an information handling system platform.

A method for controlling circuit modules within a chip is provided, wherein the circuit modules includes at least one processor and at least one network module, and the method includes: obtaining a plurality of temperature-related information of the circuit modules; and allocating power limits or throughput limits of the circuit modules according to the temperature-related information of the circuit modules, respectively.

A voltage stacked system that includes a stack of near threshold computing (NTC) chips for achieving inter-chip communication with simple wires as interconnections is disclosed. The chips include at least two secondary supply voltages and at least a secondary ground voltage electrically coupled to the stack of the chips arranged in series. The secondary supply and ground voltages are tapped in a predefined sequence at one or more predefined access points in the stack to generate two versions of an internal voltage within each of the chips. Each of the two versions of the internal voltage is a voltage difference between respective supply voltages and ground voltages, and the two have a set voltage shift such that the chips in the stack have supply voltages overlapping with those in the neighboring chips. Optionally, the two voltages are boosted to further higher voltages as needed using charge pumps.