A low-latency network interface and complementary data management protocols are disclosed in this specification. The data management protocols reduce dedicated control exchanges between the network interface and a corresponding host computing system by consolidating control data with network data. The network interface may also facilitate port forwarding and data logging without an external network switch.

A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Provided are an array substrate and driving method thereof, and a display apparatus. The array substrate comprises multiple storage electrode lines (1) each of which comprises at least two storage electrode signal input terminals (11). The array substrate can improve the driving capability of the storage electrode signals on the storage electrode lines (1).

The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA).

Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

A computer-implemented method includes writing, by a producer, data to one or more buffers. The one or more buffers include a plurality of cells and together form a circular buffer, and an input cursor indicates which cell of the plurality of cells the producer writes to. The method further includes reading, by a consumer, data from the one or more buffers, where an output cursor indicates which cell of the plurality of cells the consumer reads from. It is detected that the consumer is overrun by the producer. A throughput of the consumer is compared to a throughput of the producer, responsive to detecting that the consumer is overrun by the producer. The output cursor is synchronized to a new position, by a computer processor, where the new position is selected based on comparing the throughput of the consumer to the throughput of the producer.

A computer-implemented method includes writing, by a producer, data to one or more buffers. The one or more buffers include a plurality of cells and together form a circular buffer, and an input cursor indicates which cell of the plurality of cells the producer writes to. The method further includes reading, by a consumer, data from the one or more buffers, where an output cursor indicates which cell of the plurality of cells the consumer reads from. It is detected that the consumer is overrun by the producer. A throughput of the consumer is compared to a throughput of the producer, responsive to detecting that the consumer is overrun by the producer. The output cursor is synchronized to a new position, by a computer processor, where the new position is selected based on comparing the throughput of the consumer to the throughput of the producer.

A method for predicting characteristics of semiconductor devices includes collecting first data for a plurality of first characteristics from first semiconductor devices already in mass production, and collecting second data for the first characteristics and third data for a plurality of second characteristics from at least one second semiconductor device manufactured as an experimental sample before beginning the mass production. A covariance matrix is then obtained based on the first, second, and third data, and a mean vector for third semiconductor devices to be in the mass production is determined. Prediction data for third semiconductor devices is then generated based on the covariance matrix and the mean vector.