A memory controller includes a mapping data control unit configured to interrupt the generation of the additional mapping data, when during generation of additional mapping data, an operation for an address identical to a logical block address in the additional mapping data is performed, and to generate dummy mapping data. The additional mapping data may include mapping information indicating a mapping relationship between a logical block address and a physical block address.

Virtual memory address space is divided according to areas of the virtual memory address and allocating some areas to low-cost volatile memory (such as RAM) when the memory areas are not required by an application to be stored in non-volatile memory, such as NVDIMM. A loader mechanism creates and maintains a layout address table in non-volatile memory for recovery from an unexpected reset.

Methods, systems and computer program products for high-availability computing. In a computing configuration comprising a primary node, a first backup node, and a second backup node, a particular data state is restored to the primary node from a backup snapshot at the second backup node. Firstly, a snapshot coverage gap is identified between a primary node snapshot at the primary node and the backup snapshot at the second backup node. Next, intervening snapshots at the first backup node that fills the snapshot coverage gap are identified and located. Having both the backup snapshot from the second backup node and the intervening snapshots from the first backup node, the particular data state at the primary node is restored by performing differencing operations between the primary node snapshot, the backup snapshot from the second backup node, and the intervening snapshots of the first backup node.

A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

A method of integrating data across multiple data stores is provided. The method includes ingesting diverse data from multiple data sources and reconciling the ingested diverse data by updating semantic models based on the ingested diverse data. The method further includes storing the ingested diverse data based on one or more classification of the data sources according to the semantic models and automatically generating scalable service endpoints that are semantically consistent according to the classification of the data sources. The generated scalable service endpoints are application programming interfaces. The method also includes determining a protocol based on the scalable service endpoints in response to receiving a call from the one or more recipient systems and responding to the call from the one or more recipient systems by providing data in the classification of the data sources.

A method of integrating data across multiple data stores is provided. The method includes ingesting diverse data from multiple data sources and reconciling the ingested diverse data by updating semantic models based on the ingested diverse data. The method further includes storing the ingested diverse data based on one or more classification of the data sources according to the semantic models and automatically generating scalable service endpoints that are semantically consistent according to the classification of the data sources. The generated scalable service endpoints are application programming interfaces. The method also includes determining a protocol based on the scalable service endpoints in response to receiving a call from the one or more recipient systems and responding to the call from the one or more recipient systems by providing data in the classification of the data sources.

The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.

In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.