A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

Modifying a clone image of a dataset, including: generating, based on metadata describing one or more updates to a dataset, a tracking copy of replica data on a target data repository; generating, after receiving an indication to begin accepting modifications to the tracking copy of the replica data, a cloned image of the dataset that is modifiable without modifying the tracking copy of the replica data; and responsive to a storage operation directed to the target data repository, modifying the cloned image of the dataset without modifying the tracking copy of the replica data.

Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.

An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

A reference snapshot selection technique is configured to select a reference snapshot resolution algorithm used to determine an appropriate reference snapshot that may be employed to perform incremental snapshot replication of workload data between primary and secondary sites in a data replication environment. A reference resolution procedure is configured to process a set of constraints from the data replication environment to dynamically select the reference snapshot resolution algorithm based on a figure of merit that satisfies administrative constraints to reduce or optimize resource utilization in the data replication environment.

According to one embodiment, while a memory card is in a second operation mode, a host controller monitors a reset signal for the second operation mode and detects that an error occurs in the second operation mode in the condition that a period of time during which both a card presence signal and the reset signal are asserted continues for a first period of time or longer. The host controller generates a first interrupt signal for starting a first driver in response to the detection of the occurrence of the error. The first driver, when started by the first interrupt signal, changes the operation mode of the memory card from the second operation mode to a first operation mode by controlling the host controller.

When a host-slave system including a host device and a slave device transitions to a power-down mode, the host device drives a CMD line in order of a high level, a low level, and a high level, and stops supplying a clock signal after a predetermined time elapses. During a power-down mode period, the slave device stops supplying a power to a back-end module. When the host device resumes the supply of the clock signal, the host-slave system returns from the power-down mode.

A flash memory lifespan is increased, using a simple process, while restricting an increase in cost. A flash memory management device includes a flash memory having data retaining areas, which retain data, and short-lived areas, which have the same cell structure as the data retaining areas and data retaining properties inferior to those of the data retaining areas, wherein data of the short-lived areas are confirmed by a controller, and data retained in the data retaining areas are refreshed in accordance with the confirmed data of the short-lived areas.

A server includes a processor programmed to: acquire first metadata of a first media file recorded by a first mobile device; acquire second metadata of a second media file recorded by a second mobile device; determine that the first media file and the second medial file are likely recordings of the same event when a similarity exceeds a first threshold. The processor is further programmed to, when the first media file and the second medial file are likely recordings of the same event: determine, based on a comparison between the first media file and the second media file, which of the first media file and the second media file is a higher quality recording of the same event; and when the first media file is the higher quality recording, send a link to the first media file to the second mobile device.

The present invention provides a control method of a flash memory controller wherein the control method includes the steps of: selecting a first block; reading pages of the first block and determining a bit error rate or a bit error count of each page; for each of the pages, if the bit error rate or the bit error count of the page is not greater than a first threshold value, moving the data of the page into a second block; and for each of the pages, if the bit error rate or the bit error count of the page is greater than the first threshold value, moving the data of the page into a third block; wherein a number of pages corresponding to a word line of the second block is less than a number of pages corresponding to a word line of the third block.