G06F2213/00

System and method for supporting a dual role controller in a portable information handling system
11593297 · 2023-02-28 · ·

A system for supporting a dual role controller in an information handling systems configurable as a device or a host. When the information handling system is connected to another information handling system and configured for operating in a device mode, a proxy service and an agent service execute on the information handling system. Communications from the other information handling system are received by the proxy service and sent to the agent service, which translates generic requests into application specific requests and commands. Device functions like MTP (storage), Webcam (streaming) and generic-USB commands are enabled in device mode for virtual desktop interface (VDI) or hardware isolated applications.

SYSTEM AND METHOD FOR SUPPORTING A DUAL ROLE CONTROLLER IN A PORTABLE INFORMATION HANDLING SYSTEM
20220131949 · 2022-04-28 ·

A system for supporting a dual role controller in an information handling systems configurable as a device or a host. When the information handling system is connected to another information handling system and configured for operating in a device mode, a proxy service and an agent service execute on the information handling system. Communications from the other information handling system are received by the proxy service and sent to the agent service, which translates generic requests into application specific requests and commands. Device functions like MTP (storage), Webcam (streaming) and generic-USB commands are enabled in device mode for virtual desktop interface (VDI) or hardware isolated applications.

ON-CHIP NVM ISP EMULATION IN FPGA

An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

BI-DIRECTIONAL SIGNAL TRANSMISSION CONNECTION CABLE
20220121591 · 2022-04-21 ·

A bi-directional signal transmission connection cable is disclosed. The bi-directional signal transmission connection cable can be connected between a first and a second electronic device. The bi-directional signal transmission connection cable includes a first connection port, a second connection port, a first repeater chip, a second repeater chip and a plurality of transmission wires. The first and the second repeater chips are symmetrically disposed in the first and the second connection ports. The first repeater chip has a first set of adjustment parameters, and the second repeater chip has a second set of adjustment parameters. Thus, when a signal is transmitted between the first and the second electronic devices via the first connection port, the second connection port, and the plurality of transmission wires, the signal is adjusted by the first set of adjustment parameters and the second set of adjustment parameters.

Bi-directional signal transmission connection cable
11308014 · 2022-04-19 · ·

A bi-directional signal transmission connection cable is disclosed. The bi-directional signal transmission connection cable can be connected between a first and a second electronic device. The bi-directional signal transmission connection cable includes a first connection port, a second connection port, a first repeater chip, a second repeater chip and a plurality of transmission wires. The first and the second repeater chips are symmetrically disposed in the first and the second connection ports. The first repeater chip has a first set of adjustment parameters, and the second repeater chip has a second set of adjustment parameters. Thus, when a signal is transmitted between the first and the second electronic devices via the first connection port, the second connection port, and the plurality of transmission wires, the signal is adjusted by the first set of adjustment parameters and the second set of adjustment parameters.

Management of data transfers

Systems and methods for recording and communicating engine data are provided. One example aspect of the present disclosure is directed to a method for communicating engine data. The method includes receiving data. The method includes separating the data into categories. For one or more categories, the method includes creating a file including the separated data. For one or more categories, the method includes naming the file, at least in part, based on the category and based on a file naming convention. The method includes prioritizing the created files. The method includes transmitting an identification file comprising identification information for a wireless communication unit and the file naming convention. The method includes transmitting the created files based on the priority.

Executing distributed memory operations using processing elements connected by distributed channels

A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

Storage device and method of controlling link state thereof

A method of controlling a link state of a communication port of a storage device according to the present inventive concepts includes setting the link state of the communication port to a link active state that can exchange data with a host, determining a holding time of a first standby state among link states of the communication port, changing the link state of the communication port to the first standby state, monitoring whether an exit event occurs during the holding time from the time when a transition to the first standby state occurs, and in response to an exit event not occurring during the holding time, changing the link state of the communication port to a second standby state. A recovery time from the first standby state to the link active state is shorter than a recovery time from the second standby state to the link active state.

Monitoring device for recovering a stalled bus
10565088 · 2020-02-18 · ·

According to some possible implementations, a monitoring device may receive a set of inputs from one or more drivers of a device connected to a bus. The one or more drivers may be capable of driving a bus line of the bus, and the bus may connect multiple devices capable of driving the bus line. The monitoring device may determine a length of time over which the set of inputs maintains a value indicating that the bus is not idle. The monitoring device may compare the length of time and a threshold. The monitoring device may output a signal based on comparing the length of time and the threshold.

Data-transfer test mode

Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.