An analog sensor with digital compensation function includes a deformation part generating a deformation relating to a pressure sensed by the analog sensor; a strain gauge connected to the deformation part and generating a change in resistance relating to the deformation; a strain gauge bridge connected to the strain gauge and transferring the change in the resistance of the at least one strain gauge to output a first analog signal; and an analog-to-digital conversion module converting the first analog signal to a first digital signal, representative of weight. A signal processing and output circuit compensates the first digital signal and converts it into a second analog signal.

An analog sensor with digital compensation function includes a deformation part generating a deformation relating to a pressure sensed by the analog sensor; a strain gauge connected to the deformation part and generating a change in resistance relating to the deformation; a strain gauge bridge connected to the strain gauge and transferring the change in the resistance of the at least one strain gauge to output a first analog signal; and an analog-to-digital conversion module converting the first analog signal to a first digital signal, representative of weight. A signal processing and output circuit compensates the first digital signal and converts it into a second analog signal.

Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.

Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R.sub.on or R.sub.off to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating, the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating, the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

A computing element array system includes an array of computing elements connected by connections. Each computing element has a control circuit, a storage circuit, and an operation circuit and the connections each connect two computing elements. The storage circuit can input and store a data packet comprising a data value and a target-tag from one of the connections. The operation circuit can perform an operation on the data value to form a processed data value. The target-tag specifies a computing element to perform the operation on the data value. The control circuit can identify a computing element from the target-tag, enable the operation circuit to process the data value if the identified computing element matches the computing element, modify the data packet to comprise the processed data value, and enable the output of the modified data packet on one of the connections.

Examples disclosed herein relate to averaging modules. For example, a method may include obtaining, by an analog-to-digital converter (ADC), a plurality of samples of an input analog signal. The method may also include determining, by an averaging module, a sum value of the plurality of samples, such that a set of most significant bits of the sum value represent an average value of the plurality of samples. The method may further include determining the average value based at least on the set of most significant bits, and outputting the average value to a bus coupled to a memory module.