Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.

Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.

The present disclosure describes a computer using a combination of analogue and digital components/elements used in a cohesive manner. Depending on the signals and data the computer manipulates, the analog processing elements and digital processing elements can be used separately, independently or in combination to optimize the computational results and the performance of the computer.

The present disclosure describes a computer using a combination of analogue and digital components/elements used in a cohesive manner. Depending on the signals and data the computer manipulates, the analog processing elements and digital processing elements can be used separately, independently or in combination to optimize the computational results and the performance of the computer.

Techniques are provided for efficient matrix multiplication using in-memory analog parallel processing, with applications for neural networks and artificial intelligence processors. A methodology implementing the techniques according to an embodiment includes storing two matrices in-memory. The first matrix is stored in transposed form such that the transposed first matrix has the same number of rows as the second matrix. The method further includes reading columns of the matrices from the memory in parallel, using disclosed bit line functional read operations and cross bit line functional read operations, which are employed to generate analog dot products between the columns. Each of the dot products corresponds to an element of the matrix multiplication product of the two matrices. In some embodiments, one of the matrices may be used to store neural network weighting factors, and the other matrix may be used to store input data to be processed by the neural network.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

A function generator provides a first signal unit for the delivery of a first signal at a first output. The function generator provides a second signal unit for the delivery of a second signal at a second output. The function generator provides a calibration unit for the generation of a test signal, wherein the test signal can be supplied to the first signal unit and/or to the second signal unit. A comparison unit is connected downstream of the first signal unit and/or the second signal unit. The comparison unit compares the test signal delivered at the first output and/or at the second output with a calibration signal, wherein the output signal of the comparison unit can be supplied to the calibration unit.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.