A relay device transfers a plurality of original data fragments corresponding to a plurality of secret sharing values of original data to a plurality of secure computation devices, transfers, to each of the secure computation devices, a request to send a result fragment based on a secure computation result corresponding to any one of the original data fragments, and transfers the result fragment. The relay device controls timing with which the original data fragments are transferred and timing with which the request to send is transferred.

A relay device transfers a plurality of original data fragments corresponding to a plurality of secret sharing values of original data to a plurality of secure computation devices, transfers, to each of the secure computation devices, a request to send a result fragment based on a secure computation result corresponding to any one of the original data fragments, and transfers the result fragment. The relay device controls timing with which the original data fragments are transferred and timing with which the request to send is transferred.

A method (and structure) includes receiving a challenge for an authentication, in a chip having stored in a memory device therein a secret to be used in an authentication attempt of the chip by an external agent. The chip includes a hardware processing circuit to sequentially perform a processing related to the secret. The secret is retrieved from the memory device and processed in the hardware processing circuit in accordance with information included in the received challenge. The result of the processing in the hardware processing circuit is transmitted as a response to the challenge. The hardware processing circuit executes in a parallel manner, thereby reducing a signal that can be detected by an adversary attempting a side channel attack to secure the secret.

A cryptographical apparatus for converting input bit sequences, whose overflow-free arithmetic addition results in a secret, into output bit sequences whose logic XORing results in the secret. The apparatus comprises a data interface for providing a first input bit sequence and a second input bit sequence and a processing circuit configured to a) gate the first input bit sequence and the second input bit sequence to obtain a logic result indicating overflow bit positions at which both the first input bit sequence and the second input bit sequence have a value of one; and to b) change the first and/or second input bit sequence at at least one overflow bit position. The processing circuit is configured to repeatedly perform steps a) and b) by using the respectively changed input bit sequences, until the logic result indicates no further overflow bit position and the output bit sequences are obtained.

A cryptographical apparatus for converting input bit sequences, whose overflow-free arithmetic addition results in a secret, into output bit sequences whose logic XORing results in the secret. The apparatus comprises a data interface for providing a first input bit sequence and a second input bit sequence and a processing circuit configured to a) gate the first input bit sequence and the second input bit sequence to obtain a logic result indicating overflow bit positions at which both the first input bit sequence and the second input bit sequence have a value of one; and to b) change the first and/or second input bit sequence at at least one overflow bit position. The processing circuit is configured to repeatedly perform steps a) and b) by using the respectively changed input bit sequences, until the logic result indicates no further overflow bit position and the output bit sequences are obtained.

A method and a system of selective encryption of a test dataset is disclosed. In an embodiment, the method may include determining a relevancy grade associated with each of a plurality of datapoints within a test dataset by comparing the test dataset with a common heat map, wherein the common heat map is generated using a plurality of training datasets. The method may further include calculating, based on the relevancy grade, an encryption level associated with each of the plurality of datapoints. The method may further include selectively encrypting at least one datapoint from the plurality of datapoints based on the encryption level associated with each of the plurality of datapoints. The at least one data point is rendered to a user after being decrypted.

A method and a system of selective encryption of a test dataset is disclosed. In an embodiment, the method may include determining a relevancy grade associated with each of a plurality of datapoints within a test dataset by comparing the test dataset with a common heat map, wherein the common heat map is generated using a plurality of training datasets. The method may further include calculating, based on the relevancy grade, an encryption level associated with each of the plurality of datapoints. The method may further include selectively encrypting at least one datapoint from the plurality of datapoints based on the encryption level associated with each of the plurality of datapoints. The at least one data point is rendered to a user after being decrypted.

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

A public value 2.sup.σ/m is obtained, and secure computation of public value division [x]/(2.sup.σ/m) using a secret share value [x] and the obtained public value 2.sup.σ/m is performed, so that a secret share value [mx].sub.r of a value obtained by right-shifting mx by σ bits is obtained and output. Here, x is a real number, [•] is a secret share value of •, σ is a positive integer that is the number of bits indicating a right shifting amount, and m is a real number.