The present invention provides a gate driver on array (GOA) circuit, a display panel, and a threshold voltage compensating method for a thin film transistor (TFT). The GOA circuit only includes five TFTs and achieves a super narrow bezel of a display panel, and uses a dual-gate electrode structure as the first thin film transistor (T1). Therefore, a threshold voltage (Vth) in the GOA circuit is controlled by a top gate (the top gate connected to a node in the GOA circuit) and a bottom gate (adjustable voltage source (VLS)). Specifically, when the Vth of the TFT negatively shifts overall, the bottom gate voltage can be adjusted negatively. When the Vth of the TFT positively shifts, the bottom gate voltage can be adjusted negatively to stabilize the GOA circuit, increase a lifespan thereof, reduce leakage of a first node (Q) such that the GOA circuit can output ultra-wide pulse signals.

A GOA circuit includes GOA circuit units coupled in series. Each GOA circuit unit includes an input control module, an output control module, a pull-down module, and a pull-up holding module. The input control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Each GOA circuit unit includes ten transistors. Because the GOA circuit unit proposed by the present invention comprises fewer transistors, it is good for being used in displays with a narrow bezel. In addition, the GOA circuit unit comprises an input control module comprising a second transistor and a third transistor controlled by a first gate turn-on signal. A first transistor and the second transistor are connected in series, and the third transistor and a fourth transistor are connected in series, which reduces leakage current. It provides a beneficiary effect that the stability of the GOA circuit unit is improved.

A GOA circuit includes GOA circuit units. The GOA circuit units at every two stages share a pull-down circuit. The pull-down circuit includes a first transistor, a second transistor and a third transistor. The present invention uses fewer transistors for the GOA circuit and lower the frequency of the first and second clock signals. The decrease in the frequency of the first and second clock signals helps a decrease in the frequency of charge and discharge to the parasitic capacitance and further a reduction in overall power consumption of the GOA circuit.

A pixel driving circuit comprises a data writing circuit, a driving circuit, a light emitting control circuit, a compensation circuit and a storage circuit, the data writing circuit is coupled to the driving circuit, for writing a data signal into the driving circuit; the driving circuit is coupled to a first power source end and a light-emitting sub-circuit through the light emitting control circuit, for inputting, under control of the light emitting control circuit, driving current into the light-emitting sub-circuit according to the data signal; the compensation circuit is coupled to the driving circuit; the storage circuit is coupled between the first power source end and the driving circuit; and the data writing circuit and the compensation circuit includes at least two transistors, wherein in the data write circuit and the compensation circuit, at least one transistor is a low-temperature polysilicon transistor, and at least one transistor is an oxide transistor.

The present disclosure provides a gate driving circuit in which a node potential compensation unit connected to a touch switch terminal is provided between pull-up nodes of two stages of shift register units of each preset unit group. The node potential compensation unit may compensate for, under the control of both of a pull-up node of a previous stage of shift register unit and the touch switch terminal, a potential of a pull-up node of a next stage of shift register unit, and may enable the potential of the pull-up node of the next stage of shift register unit to be in a stable state, so as to improve the stability of the potential of the gate turn-on signal output by the next stage of shift register unit, thereby enabling a TFT of a pixel region in a corresponding line to be normally turned on and improving a display performance.

A shift register, a drive method, a drive circuit, a display substrate, and a display device are provided. The shift register includes an input unit, a first control unit, a second control unit, an output unit, and a voltage stabilizing unit. The input unit is configured to provide a signal of a signal input end to a first node and a signal of a first power supply end to a second node. The first control unit is configured to control a signal of a fourth node. The second control unit is configured to provide a signal of a second power supply end to the first node. The output unit is configured to provide the signal of the first or the second power supply end to the output end. The voltage stabilizing unit is connected to the first node, fifth node, the output end, and the first power supply end.

A pixel driving circuit, a driving method, a display panel and a display device are provided. The pixel driving circuit include a driving module, configured to drive a light-emitting element to emit light, wherein a control terminal of the driving module is electrically connected to a first node, and a first terminal is electrically connected to a second node; a data writing module, configured to write data signals, wherein a control terminal of the data writing module is electrically connected with a first scan signal line, and a first terminal is electrically connected with a data signal terminal; and a coupling module, configured to couple the data signals to the first terminal of the driving module, wherein a first terminal of the coupling module is electrically connected to a second terminal of the data writing module, and a second terminal is electrically connected to the second node.

The present invention discloses a LCD device and a LCD. The LCD device includes: a power supply unit, a gate driver circuit, a source driver circuit and a plurality of data lines and scan lines that interlace mutually, the gate driver circuit includes a plurality of gate driver integrated circuits, the source driver circuit includes a plurality of source driver integrated circuits, the power supply unit is applied to generate a gate high voltage and a gate low voltage; the power supply unit transmits the gate high voltage to a plurality of gate driver integrated circuits by a plurality of first transmission routes, the power supply unit transmits the gate low voltage to a plurality of gate driver integrated circuits by a plurality of second transmission routes, the plurality of gate driver integrated circuits provide scanning signals to the plurality of scan lines in turn.

A display device includes a scan write line for receiving a scan write signal, a first driving voltage line for receiving a first driving voltage, a first data line for receiving first data voltages, a second data line for receiving second data voltages, and a sub-pixel connected to the scan write line, the first data line, the second data line, and the first driving voltage line, wherein the sub-pixel includes a light emitting element connected to the first driving voltage line, a constant current generator configured to apply a driving current to the light emitting element according to a first data voltage among the first data voltages of the first data line, and a light emission period controller configured to control a light emission period of the light emitting element according to a second data voltage among the second data voltages of the second data line.

A display apparatus, a gate driver and an operation method thereof are provided. The gate driver includes a first input buffer and a gate line driving circuit. An input terminal of the first input buffer is configured to receive a timing control signal from the outside of the gate driver. The gate line driving circuit is coupled to an output terminal of the first input buffer. The gate line driving circuit is configured to scan a plurality of gate lines of the display panel based on the control of the timing control signal. An output impedance of the first input buffer is correspondingly adjusted according to the coupling noise of the gate driver.