Disclosed are a display panel and a display device. The display panel includes a display area and a non-display area surrounding the display area. The display area includes scan lines arranged in a second direction and each extending in a first direction, data lines arranged in the first direction and each extending in the second direction, and pixel driver circuits defined by the scan lines and the data lines intersecting each other, the first direction intersecting the second direction. The non-display area includes a step area and a compensation unit, and the compensation unit is located between the step area and a last row of pixel driver circuits. The compensation unit is connected to a corresponding data line and configured to transmit a leakage current compensation signal to the data line.

A light emission apparatus is provided. The apparatus comprises a plurality of pixels that each include a light emission element, and a signal supply unit that supplies to each of the plurality of pixels a signal voltage that accords with inputted image data. Each of the plurality of pixels comprises a first transistor configured to control an amount of current that flows in the light emission element, and a second transistor disposed between a signal line on which the signal voltage is supplied and a gate electrode of the first transistor and, in an on state, write in the gate electrode the signal voltage. The signal supply unit adjusts the signal voltage in accordance with a frame rate.

A display panel, a display control method and a display device are provided. The display panel includes a display region and a non-display region, and a plurality of pixel units distributed in the display region in an array. Each pixel unit of the plurality of pixel units includes sub-pixels of at least three colors. The display panel also includes a control unit disposed in the non-display region and configured, in a first display mode, to control the sub-pixels of a same color of at least two pixel units of the plurality of pixel units to share a data signal.

A gate driver circuit and a display device including the same have a voltage difference between output lines of the gate driver circuit that is reduced. To this end, a first gate driver is disposed on one side of a display panel, while a second gate driver is disposed on side of the display panel opposite the one side. An odd-numbered output line of the first gate driver is connected to an even-numbered output line of the second gate driver, while an even-numbered output line of the first gate driver is connected to an odd-numbered output line of the second gate driver. Therefore, the voltage difference between the output lines of the gate driver circuit is minimized or reduced.

A display apparatus according to embodiments of the present disclosure includes a display panel including at least one light emitting element that emits light according to a difference in respective voltages applied to an anode electrode and a cathode electrode, and including a plurality of pixels that are connected to a plurality of data lines, a plurality of gate lines, and a plurality of light emitting control lines, wherein a reset voltage is supplied to the anode electrode, a data driver for supplying data signals to the data lines, a gate driver for supplying gate signals to the gate lines, and supplying a light emitting control signal to each of the light emitting control lines, and a timing controller for controlling the data driver and the gate driver, and enabling the reset voltage to be supplied in sync with a plurality of non-light emitting periods of the light emitting control signal included in one frame.

An electroluminescent display device includes a pixel circuit having transistors, and a gate driving circuit providing an emission signal, a first scan signal, and a second scan signal to the pixel circuit. The gate driving circuit includes an emission signal generating circuit for applying the emission signal to a gate electrode of at least one of the transistors, a first scan signal generating circuit for applying the first scan signal to a gate electrode of at least one of the transistors, and a second scan signal generating circuit for applying the second scan signal to a gate electrode of at least one of the transistors. The first scan signal generating circuit receives the emission signal and a voltage of a QB node of the second scan signal generating circuit, and the emission signal generating circuit and the first scan signal generating circuit include an n-type transistor and a p-type transistor.

A gate driver and a display device including the gate driver are discussed. The gate driver in one example includes a shift register configured to control charging and discharging of a Q node and a QB node, and i output buffers sequentially connected to the shift register, where i is a natural number of at least 2. Each output buffer is configured to output a gate signal to a corresponding gate line in response to a voltage of the Q node and a voltage of the QB node. The gate driver further includes a dummy output buffer connected to the last stage of the shift register and configured to output a dummy signal to a dummy line in response to the voltage of the Q node.

A display device includes a display panel having scan lines, data lines, and sub-pixels disposed therein; a scan driver which drives the scan lines; and a data driver which drives the data lines. Each of the sub-pixels includes: a light emitting element; a driving transistor which drives the light emitting element; a 3-1th transistor electrically connected between a first node of the driving transistor and a high potential voltage; a 1-1th transistor and a 1-2th transistor each electrically connected between a second node of the driving transistor and a 1-1th or 1-2th data line, respectively; a second transistor electrically connected between a third node of the driving transistor and an initialization voltage line; a first capacitor connected between the second node and an anode electrode of the light emitting element; and a second capacitor connected between the high potential voltage and the anode electrode.

Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage blocks for outputting n gate signals (n is a positive integer). Each stage block includes each start stage circuit including a blank start circuit for receiving a block selection signal, and a signal output circuit for outputting a carry signal and a gate signal; and a plurality of normal stage circuits connected to each start stage circuit.

A light emitting display apparatus comprises a gate driver including stages connected with gate lines provided in a display area and a dummy stage connected with dummy gate lines provided in a non-display area, a sensing unit connected with the dummy stage connected with at least two dummy gate lines provided in the non-display area, and a controller connected with the sensing unit, wherein the dummy stage sequentially outputs at least two gate pulses, the sensing unit senses a voltage of a Q node to which a Q node signal for allowing the gate pulses to be output from the dummy stage is supplied, and the controller supplies a compensation signal based on the voltage to the stages.