A driving circuit includes a gamma chip configured to provide a plurality of initial binding point voltages; the gamma chip including a first type of output terminals and a second type of output terminals, currents corresponding to the initial binding point voltages outputted by the first type of output terminals being less than a preset driving current; and currents corresponding to the initial binding point voltages outputted by the second type of output terminals being greater than the preset driving current; and a data driving chip including a processor and a plurality of operational amplifiers.

An integrated circuit device includes a drive circuit that outputs a first drive waveform signal for dot matrix display and a second drive waveform signal for segment display, a first output terminal, a second output terminal, and a control circuit that controls the drive circuit. The drive circuit outputs the first drive waveform signal to the first output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the first output terminal when its terminal is set as the output terminal for segment display. The drive circuit outputs the first drive waveform signal to the second output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the second output terminal when its terminal is set as the output terminal for segment display.

An integrated circuit device includes a drive circuit that outputs a first drive waveform signal for dot matrix display and a second drive waveform signal for segment display, a first output terminal, a second output terminal, and a control circuit that controls the drive circuit. The drive circuit outputs the first drive waveform signal to the first output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the first output terminal when its terminal is set as the output terminal for segment display. The drive circuit outputs the first drive waveform signal to the second output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the second output terminal when its terminal is set as the output terminal for segment display.

A driving circuit includes a gamma chip configured to provide a plurality of initial binding point voltages; the gamma chip including a first type of output terminals and a second type of output terminals, currents corresponding to the initial binding point voltages outputted by the first type of output terminals being less than a preset driving current; and currents corresponding to the initial binding point voltages outputted by the second type of output terminals being greater than the preset driving current; and a data driving chip including a processor and a plurality of operational amplifiers.

A wire component includes a plurality of working signal lines and a plurality of transmitting lines. The working signal lines are configured to respectively provide a plurality of working signals to a driving circuit, and phases of the working signals at least partially lag each other sequentially. The transmitting lines are configured to respectively transmit the working signals, and a portion of the transmitting lines crosses the working signal lines. A first working signal line is configured to provide a first working signal; a second working signal line is configured to provide a second working signal; the first working signal immediately lags the second working signal, and the first working signal line and the second working signal line are arranged with another working signal line therebetween.

A display driver (100) includes terminals (TSEG1 and TSEG2) and a drive circuit (130). The terminal (TSEG1) can be connected to a segment electrode (ESEG1). The terminal (TSEG2) can be connected to a segment electrode (ESEG2) whose area is larger than the area of the segment electrode (ESEG1). The drive circuit (130) outputs a PWM segment drive signal (SSEG1) to the terminal (ESEG1), and outputs a PWM segment drive signal (SSEG2) to the terminal (TSEG2). When the same effective voltage is applied to the segment electrode (ESEG1) and the segment electrode (ESEG2), the duty ratio of the segment drive signal (SSEG1) is smaller than the duty ratio of the segment drive signal (ESEG2).

An array substrate and a display panel are provided. The array substrate includes an enable signal input terminal, a preset electric potential input terminal, and a connection resistor. The enable signal input terminal is for inputting an enable signal. The preset electric potential input terminal is for inputting a preset electric potential. The connection resistor is connected to the enable signal input terminal and the preset electric potential input terminal, and a resistance value of the connection resistor is a predetermined multiple of a resistance value of the enable signal input terminal. In the present disclosure, the enable signal can be input through the preset electric potential input terminal.

A wire component includes a plurality of working signal lines and a plurality of transmitting lines. The working signal lines are configured to respectively provide a plurality of working signals to a driving circuit, and phases of the working signals at least partially lag each other sequentially. The transmitting lines are configured to respectively transmit the working signals, and a portion of the transmitting lines crosses the working signal lines. A first working signal line is configured to provide a first working signal; a second working signal line is configured to provide a second working signal; the first working signal immediately lags the second working signal, and the first working signal line and the second working signal line are arranged with another working signal line therebetween.

An array substrate and a display panel are provided. The array substrate includes an enable signal input terminal, a preset electric potential input terminal, and a connection resistor. The enable signal input terminal is for inputting an enable signal. The preset electric potential input terminal is for inputting a preset electric potential. The connection resistor is connected to the enable signal input terminal and the preset electric potential input terminal, and a resistance value of the connection resistor is a predetermined multiple of a resistance value of the enable signal input terminal. In the present disclosure, the enable signal can be input through the preset electric potential input terminal.

A display driver (100) includes terminals (TSEG1 and TSEG2) and a drive circuit (130). The terminal (TSEG1) can be connected to a segment electrode (ESEG1). The terminal (TSEG2) can be connected to a segment electrode (ESEG2) whose area is larger than the area of the segment electrode (ESEG1). The drive circuit (130) outputs a PWM segment drive signal (SSEG1) to the terminal (ESEG1), and outputs a PWM segment drive signal (SSEG2) to the terminal (TSEG2). When the same effective voltage is applied to the segment electrode (ESEG1) and the segment electrode (ESEG2), the duty ratio of the segment drive signal (SSEG1) is smaller than the duty ratio of the segment drive signal (ESEG2).