An electronic system includes: a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; and a memory subsystem, coupled to the high speed local memory, including: a module memory controller configured to access the operational data for the processor and the high speed local memory, a local cache controller, coupled to the module memory controller, including a fast control bus configured to store the operation data, with critical timing in a first tier memory, and a memory tier controller, coupled to the local cache controller, including a reduced performance control bus configured to store the operation data with non-critical timing in a second tier memory.

An electronic apparatus includes a base that includes a flat portion and a side wall provided upright on a part of an outer edge of the flat portion, a printed circuit board disposed in the base and including a device, and a cover covering the base. The base includes a hole that is contiguous to the side wall and provided in the flat portion, a support portion, one end of the support portion being supported by the side wall, and a positioning member provided on the support portion and positioning the cover with respect to the base.

A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

A system and method for thermal management of a memory device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached. The thermal control module may then begin tracking memory thermals or initiate thermal management operations based on the signal and history of memory device temperatures over time.

A system and method for thermal management of a memory device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached. The thermal control module may then begin tracking memory thermals or initiate thermal management operations based on the signal and history of memory device temperatures over time.

Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

A solid state drive (SSD) housing assembly includes an SSD housing and an extension frame. The SSD housing includes a first extension joint and a first mounting joint. The first mounting joint is a mechanism by which the housing can be mounted to an external device. The SSD housing has the form of a rectangular case in which an SSD module is held. The extension frame includes a second extension joint and a second mounting joint. The second mounting joint is a mechanism by which the frame can be mounted to the external device. The extension frame is attachable to and detachable from the SSD housing by virtue of the first extension joint and the second extension joint.

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

A solid-state drive device is provided. The solid-state drive device includes a housing, a first circuit board, and a second circuit board. The housing includes a first side and a second side. The first side is opposite to the second side. At least one first ventilation hole is formed on the first side. At least one second ventilation hole is formed on the second side. The first circuit board is disposed in the housing. The second circuit board is disposed in the housing. The second circuit board is coupled to the first circuit board. A gap is formed between the first circuit board and the second circuit board. The first ventilation hole and the second ventilation hole correspond to the gap.