A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.

The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device includes: providing a substrate; forming a plurality of first structures extending in a first direction on the substrate; forming a sacrificial layer on sidewalls of the first structures; forming an outer spacer layer on a sidewall of the sacrificial layer; removing part of the outer spacer layer to obtain a patterned outer spacer layer that exposes part of the sacrificial layer; and removing the sacrificial layer to form air gaps between the patterned outer spacer layer and the first structures.

A storage device and an operating method of the storage device are provided. The storage device comprises a first non-volatile memory device, a second non-volatile memory device, a third non-volatile memory device a storage controller configured to control the first non-volatile memory device, the second non-volatile memory device, and the third non-volatile memory device, control the first non-volatile memory device to extract a first on-cell count value after a first soft erase operation, set first to third read level offsets of the respective first to third non-volatile memory devices based on the respective first to third on-cell count values, select the first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and transmits first to third read commands based on the selected respective first to third defense code parameter sets to the respective first to third non-volatile memory devices.

According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The interface includes data, address and control signal pins and an output pin in addition to the data, address and control signal pins. The memory module receives a first command from the memory controller via the address and control signal pins, and enters a first mode in response to the first command. The memory module in the first mode responds to at least one initialization sequence, and sends a first output signal via the output pin to indicate a status of the at least one initialization sequence to the memory controller. The memory module enters a second mode in which the memory module performs memory operations including memory read/write operations according to an industry standard. During the read/write operations, the memory module communicates data with the memory controller via the data signal pins in response to second memory commands received via the address and control signal pins. The memory module may output a second output signal related to the read/write operations via the output pin.

According to one embodiment, a semiconductor device includes a semiconductor substrate including an element region, a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which electrically couples the first-interconnect and a first well region, a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to the first interconnect, and a first circuit coupled to the second interconnect. The first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second interconnect or a short circuit between the second interconnect and the first interconnect.

Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a first transmission line and a second transmission line located over one another. A via is shown connecting the first transmission line and a second transmission line wherein a first side of the via and a side of the second transmission line are coplanar. A via is also shown connecting the first transmission line and a second transmission line wherein the second transmission line tapers downward from a line width to a via width.

A dynamic random access memory includes a main body which has a substrate portion and a light-emitting portion and a transmission port, the substrate portion includes a board and a first coating layer, the board has a light-transmittable portion and a first face, the first coating layer is coated on the first face and has an emergent light-transmittable portion corresponding to the light-transmittable portion, and the substrate portion has a memory module. The transmission port is disposed on the substrate portion and electrically connected with the memory module. The electronic device includes the dynamic random access memory and further includes a shell portion. The shell portion is covered on two opposite lateral faces of the dynamic random access memory and at least shields the light-emitting portion, and the shell portion further has a second light-transmittable portion corresponding to the emergent light-transmittable portion.

According to one embodiment, a semiconductor device includes a semiconductor substrate including an element region, a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which electrically couples the first-interconnect and a first well region, a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to the first interconnect, and a first circuit coupled to the second interconnect. The first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second interconnect or a short circuit between the second interconnect and the first interconnect.

Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.

Memory systems are disclosed. A memory system may include a plurality of memory devices and a controller in communication with the plurality of memory devices. The controller may be configured to load respective select information to at least some memory devices of the plurality of memory devices. Each memory device of the at least some memory devices may be configured to store its respective select information. Further, each memory device of the at least some memory devices may be configured to adjust, based on the stored select information and in response to receipt of a signal at the memory device, an impedance characteristic of the memory device during at least a portion of a memory device operation of another memory device of the plurality of memory devices. Associated methods and devices are also disclosed.