Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

A method of laser-writing submicron pixels with tunable circular polarization and write-read-erase-reuse capability on Bi.sub.2Se.sub.3/WS.sub.2 at room temperature, comprising the steps of applying a laser to the Bi.sub.2Se.sub.3/WS.sub.2, writing a submicron pixel, wherein the submicron pixel has a circular polarization, modifying the circular polarization, allowing the circular polarization to be tuned across a range of 39.9%, tuning photoluminescence intensity, and tuning photoluminescence peak position. A method of growing Bi.sub.2Se.sub.3/WS.sub.2 as a nano-material or two-dimensional heterostructure for laser-writing submicron pixels with tunable circular polarization and write-read-erase-reuse capability on the Bi.sub.2Se.sub.3/WS.sub.2 heterostructure at room temperature.

A sensitive amplifier and a storage device are provided, and the sensitive amplifier includes: a voltage clamp circuit which provides a stable reading voltage for the storage unit; a power switch circuit which cuts off power supply for the voltage clamp circuit when the voltage clamp circuit is not operating; a discharge circuit which discharges the voltage clamp circuit before the voltage clamp circuit operates; a pre-charge circuit which pre-charges the voltage clamp circuit when the voltage clamp circuit starts operating; and a current comparison circuit which is connected to an output of the voltage clamp circuit, compares the reading current with a reference current, and outputs a comparison result.

An application white box device utilized in conjunction with an intelligent terminal is provided. The application white box device includes a controller, a memory, and a SIM unit. The controller provides support for management of the memory and call of the SIM unit. The memory provides a physical medium for storing data and an application of the intelligent terminal. The SIM unit provides support for encryption and security authentication of the data and the application access of the intelligent terminal.

Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.

Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.

Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

An information processing system including a communication unit that acquires information related to an interaction between objects from a sensing device that detects the interaction between the objects, an emotion information database constructed by accumulating an evaluation value used when an emotion value of each object generated based on the information related to the interaction between the objects is calculated, a certification unit that certifies the sensing device and issues certification information to the sensing device, and an authentication unit that authenticates the information related to the interaction transmitted from the sensing device based on the certification information issued to the sensing device.