The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

A circuit includes a first cell in a first row of a memory array, a second cell in a second row of the memory array, and a data line perpendicular to the first row and the second row, intersecting each of the first cell and the second cell, and electrically coupled with each of the first cell and the second cell. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a read operation on the first row.

A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.

A memory device includes a clock generating circuit suitable for generating a plurality of internal clock signals based on an external clock signal during an output period of read data, in response to a read command, and a data strobe output circuit suitable for outputting a first data strobe signal to a data strobe pad in response to the internal clock signals, wherein the internal clock signals toggle regardless of the output period of the read data, in response to a test mode signal.

A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.

A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in first and second modes. The semiconductor device also includes a data processing circuit configured to latch first to fourth internal data according to first to fourth input control signals. The data processing circuit is additionally configured to generate first to fourth output data by determining the output priority of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, first to fourth rising output control signals, and first to fourth falling output control signals.

Disclosed herein is a multi-bank type semiconductor memory device which reduces current consumption of data lines. In the multi-bank type semiconductor memory device according to the present invention, the data lines between each memory bank and an input/output buffer are divided into horizontal data lines and vertical data lines. In addition, a high impedance driver is provided to drive horizontal local data of the horizontal data line to provide the horizontal local data as vertical local data of the vertical data line. Therefore, in the multi-bank type semiconductor memory device according to the present invention, even when the horizontal local data and the vertical local data are controlled at a low power voltage, degradation in overall operating speed hardly occurs. In addition, in the multi-bank type semiconductor memory device according to the present invention, current consumption in the data lines is significantly reduced.

A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.