Artificial neuromorphic circuit includes synapse and post-neuron circuits. Synapse circuit includes phase change element, first switch having at least three terminals, and second switch. Phase change element includes first and second terminals. First switch includes first, second and control terminals. Second switch includes first, second and control terminals. First switch is configured to receive first pulse signal. Second switch is coupled to phase change element and first switch, and is configured to receive second pulse signal. Post-neuron circuit includes capacitor and input terminal. Input terminal of post-neuron circuit charges capacitor in response to first pulse signal. Post-neuron circuit generates firing signal based on voltage level of capacitor and threshold voltage. Post-neuron circuit generates control signal based on firing signal. Control signal controls turning on of second switch. Second pulse signal flows through second switch to control state of phase change element to determine weight of artificial neuromorphic circuit.

There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.

In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.

A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.

According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.