Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

A semiconductor storage device includes a first wiring, a second wiring, an insulating portion, and a resistance changing film. The first wiring extends in a first direction. The second wiring extends in a second direction intersecting the first direction, and is provided at a location different from that of the first wiring in a third direction intersecting the first direction and the second direction. The insulating portion is provided between the first wiring and the second wiring in the third direction. The resistance changing film is provided between the first wiring and the second wiring in the third direction, is adjacent to the insulating film from a first side and a second side which is opposite to the first side in the first direction, and the resistance changing film being smaller than the second wiring in the first direction.

An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.

A molecular scrivener reads data from or writes data to a macromolecule and includes: a pair of shielding electrodes; a scrivener electrode between the first and second shielding electrodes and that electrically floats at a third potential that, in an absence of a charged or dipolar moiety of the macromolecule, is intermediate between the first and second potentials and changes in a presence of the charged or dipolar moiety; a dielectric layer interposed between shielding electrodes and the scrivener electrode; and a nanopore that communicates the macromolecule through the electrodes and dielectric layers. Reading data from or writing data to a macromolecule includes: sequentially receiving, at the scrivener electrode, individual moieties of the macromolecule so that the third potential responds to individual moieties; communicating the macromolecule from the scrivener electrode to the second shielding electrode and from second shielding electrode to expel the macromolecule from the nanopore.

According to one embodiment, a semiconductor memory device includes: a first and a second wirings; a third wiring disposed between them; a first phase change layer disposed between the first and the third wirings; a first conducting layer disposed on a first wiring side surface of the first phase change layer; a second conducting layer disposed on a third wiring side surface of the first phase change layer; a second phase change layer disposed between the third and the second wirings; a third conducting layer disposed on a third wiring side surface of the second phase change layer; and a fourth conducting layer disposed on a second wiring side surface of the second phase change layer. The first and the fourth conducting layers have coefficients of thermal conductivity larger or smaller than the coefficients of thermal conductivity of the second and the third conducting layers.

Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.