A semiconductor storage apparatus according to one embodiment of the present disclosure includes a plurality of memory cells and a control circuit. Each of the memory cells includes a magnetization reversal memory device and a first switch device that controls a current to flow to the magnetization reversal memory device. The control circuit performs a writing control based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the magnetization reversal memory device.

A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.

A storage device includes a power supply device including an auxiliary power supply device providing auxiliary power, configured to generate a deterioration monitoring signal indicating a degree of deterioration of the auxiliary power supply device, and configured to generate an output voltage based on external power or the auxiliary power; and a main system configured to operate based on the output voltage and perform a dump operation for backing up data in a sudden power off (SPO) situation, wherein the main system compares the degree of deterioration of the auxiliary power supply device with a preset reference value in response to the deterioration monitoring signal, and generates a voltage scaling command for controlling the power supply device to convert an average voltage level of the output voltage to a dynamic voltage scaling (DVS) level based on a result of the comparison.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

A storage system uses consumption of transfer RAM as a trigger to enter and exit burst mode. In one embodiment, the storage system stores, in volatile memory, data to be written in non-volatile memory; monitors an allocation level of the volatile memory to determine a first amount of time that the allocation level is at a first level and a second amount of time that the allocation level is at second level; enters burst mode when a ratio of the first amount of time and the second amount of time is above a first threshold; and exits burst mode when the ratio of the first amount of time and the second amount of time is below a second threshold. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

A storage system uses consumption of transfer RAM as a trigger to enter and exit burst mode. In one embodiment, the storage system stores, in volatile memory, data to be written in non-volatile memory; monitors an allocation level of the volatile memory to determine a first amount of time that the allocation level is at a first level and a second amount of time that the allocation level is at second level; enters burst mode when a ratio of the first amount of time and the second amount of time is above a first threshold; and exits burst mode when the ratio of the first amount of time and the second amount of time is below a second threshold. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The memory controller includes an encryptor to control a plurality of memory access keys respectively associated with memory regions, where each memory region is allocated to a respective client, and an access manager to receive an access request from a client, the access request including a client access key to access a memory element. The access manager looks up a memory access key from a page table attribute associated with a physical address of the memory element, and determines if the access request is valid by comparing the client access key with the memory access key associated with the memory region that includes the memory element. Based on the determination and a mode of operation, the access manager provides a response to the access request.

Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.