Disclosed is a dual inline memory module with temperature-sensing scenario modes. A plurality of volatile memory components and an EEPROM component are disposed on a module board. A plurality of LED components and a scenario-lighting controller are disposed at a radiant side of the module board. A light bar is located at the radiant side of the module board without direct installing relationship. A plurality of clamping-type heat spreaders are fastened to one another in a manner that the light bar is tightly clamped. Therein, the power of the scenario-lighting controller component is shared and linked with the power supply system of the LED components and the signals of the scenario-lighting controller component are shared and linked with the signal connection system of the EEPROM component. Accordingly, the lighting scenario performances controlled by the scenario-lighting controller accord with the sensing temperatures to adjust memory refreshing frequencies to avoid any incorrect performance caused by sensed temperature differences.

Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data is saved quickly and efficiently using backup power. Data integrity is ensured even when the reliability of backup power sources is an issue. In some embodiments, by skipping the updating and saving of system data while operating on backup power, significant reduction of time for saving critical data can be achieved. System data can be restored next time the data storage system is restarted. Improvements of data storage system reliability are thereby attained.

A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

A nonvolatile memory device includes a memory block including a plurality of cell strings each of which includes memory cells electrically coupled with word lines stacked over a substrate; a plurality of sub common sources electrically coupled to one ends of the cell strings; and a plurality of bit lines electrically coupled to the other ends of the cell strings, wherein the memory block includes sub blocks respectively corresponding to the sub common sources, and cell strings electrically coupled to the same bit line among the cell strings are included in the same sub block.

A memory device, an operating method of the memory device, and a fabricating method of the memory device are provided. A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate electrode disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.

Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

A ferroelectric static random access memory (FeSRAM) cell includes (a) first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals; (b) first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and (c) first, second, third and fourth ferroelectric capacitors, wherein the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.