A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

A storage device includes a module substrate extending in one direction, a non-volatile memory device mounted on the module substrate, a controller mounted on the module substrate, a first connector disposed at a first end of the module substrate and through which data stored in the non-volatile memory device is input/output, and a power management integrated circuit configured to control supplying of power to the controller and the non-volatile memory device. The controller is configured such that in response to a first level signal received from the first connector, the controller connects the non-volatile memory device to the first connector, and then control, after connecting the non-volatile memory device to the first connector, the power management integrated circuit to cut off supplying of the power to the controller.

Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving source code of an application, providing intermediate code based on the source code, the intermediate code including at least one instruction for profiling at least one object of the application, providing a statistics file by processing the intermediate code based on a memory profiling library, processing the statistics file based on a plurality of models to provide a list of objects, the list of objects identifying types of memory respective objects should be stored to in a hybrid main memory system, and storing modified source code that is provided based on the source code and the list of objects.

A memory load sharing system and method therefor. This system can include a platform VRM (Voltage Regulator Module) coupled to a memory channel with the platform VRM having a platform voltage input. One or more first memory modules can coupled to the platform VRM through the memory channel. Each of the first memory modules includes one or more plane connectors and a module connector, as well as a memory module VRM coupled to a module load sharing diode that is coupled to the one or more plane connectors of that first memory module. The platform VRM is coupled to a first platform load sharing diode that is coupled the plane connectors of each of the first memory modules. This platform is configured to support load sharing between the first memory modules and to provide a predetermined amount of power to each of the memory modules.

A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions is provided. A write request that request a data write to the memory device and a read request which request a data read from the memory device are inserted to a request queue. A scheduler, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition. The second partition is a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.

A storage device includes a main system; a power loss protection integrated circuit (PLP IC) configured to provide output power to the main system based on external or internal power; and an auxiliary power supply configured to provide the internal power to the PLP IC. The main system may operate in a dump mode where data is backed up in response to at least one of a first condition or a second condition being satisfied. The PLP IC may provide the output power based on the internal power in response to a sudden power off (SPO) occurring. The first condition is satisfied when the SPO occurs and an SPO time is longer than a maximum filtering time. The second condition is satisfied when the SPO occurs and a voltage level of the internal power provided by the auxiliary power supply is lower than a voltage level of a threshold voltage.

A storage device includes a main system; a power loss protection integrated circuit (PLP IC) configured to provide output power to the main system based on external or internal power; and an auxiliary power supply configured to provide the internal power to the PLP IC. The main system may operate in a dump mode where data is backed up in response to at least one of a first condition or a second condition being satisfied. The PLP IC may provide the output power based on the internal power in response to a sudden power off (SPO) occurring. The first condition is satisfied when the SPO occurs and an SPO time is longer than a maximum filtering time. The second condition is satisfied when the SPO occurs and a voltage level of the internal power provided by the auxiliary power supply is lower than a voltage level of a threshold voltage.

A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.