A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.

A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.

A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.

A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.

An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.

According to an embodiment of the present invention, there is provided a TCAM architecture in which a content-based search is conductible in such a manner that a search key to be searched for is used as an address of a memory element that makes up a TCAM cell and that an output from the memory element reflects whether a match or a mismatch is found as a result of the search. The memory element may be a look-up table.

A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.

A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.

A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.

A switching system includes a content-addressable memory (CAM) and several processing nodes. The CAM can be selectively connected to any one or more of the processing nodes during operation of the switching system, without having to power down or otherwise reboot the switching system. The CAM is selectively connected to a processing node in that electrical paths between the CAM and the processing nodes can be established, torn down, and re-established during operation of the switching system. The switching system can include a connection matrix to selectively establish electrical paths between the CAM and the processing nodes.