Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.

An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.

A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.

A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.

Systems and methods for an optical ternary content addressable memory (TCAM) is provided. In various embodiments, one or more search words can be encoded in a multi-wavelength input signal. Each bit position associated with a set of wavelengths of the input signal, each wavelength corresponding to a logic value. A plurality of copies of the input signal can be coupled to an optical search engine comprising a plurality of rows of stored words. In various embodiments, the search word may be encoded in the amplitude of a single wavelength. Each bit position can be associated with a set input waveguides, and a logic value can be encoded based on whether amplitude of the associated wavelength is detected on a respective input waveguide of the set of waveguides. A mismatch of at least one bit is indicated if light is detected on an output of the optical TCAM.

A memory device comprises a block of ranged content-addressable memory (RCAM) including multiple RCAM memory elements, wherein each RCAM memory element is accessed by content that includes two values; a search register configured to store a search value; and logic circuitry coupled to the multiple content-addressable memory elements and the search register. The logic circuitry is configured to: compare the search value of the search register to the two values of each of the multiple RCAM memory elements in parallel; and identify an RCAM memory element according to the comparison.

A memory device comprises a block of ranged content-addressable memory (RCAM) including multiple RCAM memory elements, wherein each RCAM memory element is accessed by content that includes two values; a search register configured to store a search value; and logic circuitry coupled to the multiple content-addressable memory elements and the search register. The logic circuitry is configured to: compare the search value of the search register to the two values of each of the multiple RCAM memory elements in parallel; and identify an RCAM memory element according to the comparison.