The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width C.sub.W and a depth C.sub.D, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width C.sub.W and a depth C.sub.D, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.

The present invention discloses a memory device and operation method thereof. The operation method comprises: programming a plurality of first strings of a plurality of string pairs representing a finite state machine (FSM) to an in-memory-searching (IMS) array of a memory device; programming a plurality of second strings of the string pairs to a working memory of the memory device; and programming a string representing a starting state of the FSM to a buffer of the memory device.

An enhanced TL-TCAM lookup-table hardware search engine includes a plurality of enhanced TL-TCAM cell circuits. There are m enhanced TL-TCAM cells circuits connected in parallel to form a sub-segment circuit. The word line WL, match line ML and ML_x of each enhanced TL-TCAM cell circuit in the sub-segment circuit are respectively short-connected together, the match line ML is connected to the drain electrode of an N-type transistor N15, ML_x is connected to the gate electrode of the N-type transistor N15, and the source electrode of the N-type transistor N15 is connected to ground, ML_x is connected to the drain electrode of an N-type transistor N14, the source electrode of the N-type transistor N14 is connected to ground, and the gate electrode of the N-type transistor N14 is connected to the signal line OneX_in-Sement_b, a plurality of sub-segment circuits are connected in parallel to form a word circuit.